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Designing a 5 stage pipeline using Verilog to simulate the working of 5 instructions while resolving the data hazards between them

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To run, add the code in processor.txt file to a design source file in Vivado, then add the code in testbench.txt file as a simulation source.

This is a simple design modelling how a 5 stage pipeline works while resolving data hazards by using hazard detection and forwarding units.

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Designing a 5 stage pipeline using Verilog to simulate the working of 5 instructions while resolving the data hazards between them

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