SystemVerilog: KNOWNBUG test for subroutine calls with named parameter assignment

Author: kroening

regression/verilog/functioncall/named_parameter_assignment1.desc

@@ -0,0 +1,9 @@
+CORE
+named_parameter_assignment1.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.

regression/verilog/functioncall/named_parameter_assignment1.sv

@@ -0,0 +1,12 @@
+module main;
+
+  function [31:0] my_greater(int a, int b);
+    my_greater = a > b;
+  endfunction
+
+  initial assert(my_greater(2, 1));
+  initial assert(my_greater(.a(2), .b(1)));
+  initial assert(my_greater(2, .b(1)));
+  initial assert(!my_greater(.a(1), .b(2)));
+
+endmodule