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5 changes: 2 additions & 3 deletions regression/verilog/system-functions/error1.desc
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
KNOWNBUG
CORE
error1.v
--module main
^EXIT=0$
^EXIT=10$
^SIGNAL=0$
--
^warning: ignoring
--
This doesn't parse.
2 changes: 1 addition & 1 deletion regression/verilog/system-functions/error1.v
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ module main;

parameter P = 1;

if(P!=1)
if(P==1)
$error("something is wrong");

endmodule
3 changes: 3 additions & 0 deletions src/verilog/parser.y
Original file line number Diff line number Diff line change
Expand Up @@ -1024,6 +1024,9 @@ module_or_generate_item:
{ add_attributes($2, $1); $$=$2; }
| attribute_instance_brace module_common_item
{ add_attributes($2, $1); $$=$2; }
// The next rule is not in 1800-2017, but is a vendor extension.
| attribute_instance_brace system_tf_call ';'
{ add_attributes($2, $1); $$ = $2; }
;

module_or_generate_item_declaration:
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4 changes: 4 additions & 0 deletions src/verilog/verilog_elaborate.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -902,6 +902,10 @@ void verilog_typecheckt::collect_symbols(
{
collect_symbols(to_verilog_sequence_declaration(module_item));
}
else if(module_item.id() == ID_function_call)
{
// e.g., $error
}
else
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
}
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3 changes: 3 additions & 0 deletions src/verilog/verilog_interfaces.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -335,6 +335,9 @@ void verilog_typecheckt::interface_module_item(
else if(module_item.id() == ID_verilog_sequence_declaration)
{
}
else if(module_item.id() == ID_function_call)
{
}
else
{
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
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3 changes: 3 additions & 0 deletions src/verilog/verilog_synthesis.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3424,6 +3424,9 @@ void verilog_synthesist::synth_module_item(
else if(module_item.id() == ID_verilog_sequence_declaration)
{
}
else if(module_item.id() == ID_function_call)
{
}
else
{
throw errort().with_location(module_item.source_location())
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3 changes: 3 additions & 0 deletions src/verilog/verilog_typecheck.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1972,6 +1972,9 @@ void verilog_typecheckt::convert_module_item(
{
convert_sequence_declaration(to_verilog_sequence_declaration(module_item));
}
else if(module_item.id() == ID_function_call)
{
}
else
{
throw errort().with_location(module_item.source_location())
Expand Down
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