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Verilog: KNOWNBUG test for four-valued zero extension #1327

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Merged
merged 1 commit into from
Oct 18, 2025
Merged

Verilog: KNOWNBUG test for four-valued zero extension #1327

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9 changes: 9 additions & 0 deletions regression/verilog/expressions/equality4.desc
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KNOWNBUG
equality4.v

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
zero_extend doesn't work for four-valued operands.
11 changes: 11 additions & 0 deletions regression/verilog/expressions/equality4.sv
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module main;

// The two operands are zero-extended to 8 bits.
initial assert((2'b10 + 1'sbx) === 8'bxxxxxxxx);
initial assert((2'b10 | 1'sbx) === 8'b0000001x);

// The two operands are sign-extended to 8 bits.
initial assert((2'sb10 + 1'sbx) === 8'sbxxxxxxxx);
initial assert((2'sb10 | 1'sbx) === 8'sb1111111x);

endmodule
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