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@kroening kroening commented Nov 6, 2025

This adds the missing precedences for some Verilog operators.

This adds the missing precedences for some Verilog operators.
@kroening kroening marked this pull request as ready for review November 6, 2025 21:22
@tautschnig tautschnig merged commit 4ef8c5f into main Nov 10, 2025
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@tautschnig tautschnig deleted the verilog-precedences branch November 10, 2025 10:52
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3 participants