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SystemVerilog: allow assignment of new to any class type #1393

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Merged
merged 1 commit into from
Nov 10, 2025
Merged

SystemVerilog: allow assignment of new to any class type #1393

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5 changes: 2 additions & 3 deletions regression/verilog/class/new1.desc
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Original file line number Diff line number Diff line change
@@ -1,8 +1,7 @@
KNOWNBUG
CORE
new1.sv

^EXIT=0$
^EXIT=10$
^SIGNAL=0$
--
--
The class is not yet recognized as a type.
9 changes: 9 additions & 0 deletions src/verilog/verilog_typecheck_expr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -269,6 +269,15 @@ void verilog_typecheck_exprt::assignment_conversion(
}
}

if(rhs.type().id() == ID_verilog_new)
{
if(lhs_type.id() == ID_verilog_class_type)
{
rhs = typecast_exprt{rhs, lhs_type};
return;
}
}

// "The size of the left-hand side of an assignment forms
// the context for the right-hand expression."

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