Verilog: fix integral vs. bit vector terminology #1449
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kroening
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tautschnig
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| convert_expr(expr.rhs()); | ||
| must_be_integral(expr.lhs()); | ||
| must_be_integral(expr.rhs()); | ||
| no_bool_ops(expr); |
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Some change broke two of the regression test, and the omission of no_bool_ops here seems among the most substantial changes. Or is it the removal around line 3088?
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This changes the naming of methods and error messages. The term 'integral' includes non-integer types, e.g., time variables. Many operators require operands that are integral but exclude time variables. The standard calls these "bit vector types".
tautschnig
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Dec 2, 2025
| // The result is always Boolean, and semantically | ||
| // a proper equality is performed. | ||
| expr.type()=bool_typet(); | ||
| expr.type()=bool_typet{}; |
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Add whitespace or leave unchanged entirely to keep clang-format happy.
| // integral operands only | ||
| must_be_integral(expr.lhs()); | ||
| must_be_integral(expr.rhs()); | ||
| if(expr.lhs().type().id() == ID_verilog_real || expr.lhs().type().id() == ID_verilog_shortreal) |
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tautschnig
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This changes the naming of methods and error messages. The term 'integral' includes non-integer types, e.g., time variables. Many operators require operands that are integral but exclude time variables. The standard calls these "bit vector types".