Skip to content

Conversation

@kroening
Copy link
Collaborator

No description provided.

This extracts the static get_width(...) method into a separate function,
renaming to verilog_bits(...).
@kroening kroening marked this pull request as ready for review November 19, 2024 23:50
@tautschnig tautschnig merged commit 423de3f into main Nov 20, 2024
9 checks passed
@tautschnig tautschnig deleted the verilog_lowering branch November 20, 2024 09:07
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
Verilog: extract function for lowering expressions
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants