Eliminate gtLsraInfo from GenTree

Generate TreeNodeInfo into the map when building RefPositions.
Add some new methods and flags for former gtLsraInfo functionality that's used outside of LSRA:
- GenTree::GetRegisterDstCount() (number of registers defined by a node)
- LIR::Flags::RegOptional
- gtDebugFlags::GTF_DEBUG_NODE_LSRA_ADDED

Fix #7255

Author: CarolEidt

src/jit/emitarm64.cpp

@@ -10070,11 +10070,13 @@ void emitter::emitDispImm(ssize_t imm, bool addComma, bool alwaysHex /* =false *
         printf("#");
     }
 
-    // Munge any pointers if we want diff-able disassembly
+    // Munge any pointers if we want diff-able disassembly.
+    // Since some may be emitted as partial words, print as diffable anything that has
+    // significant bits beyond the lowest 8-bits.
     if (emitComp->opts.disDiffable)
     {
-        ssize_t top44bits = (imm >> 20);
-        if ((top44bits != 0) && (top44bits != -1))
+        ssize_t top56bits = (imm >> 8);
+        if ((top56bits != 0) && (top56bits != -1))
             imm = 0xD1FFAB1E;
     }
 

src/jit/gentree.cpp

@@ -764,6 +764,61 @@ bool GenTree::gtHasReg() const
     return hasReg;
 }
 
+//-----------------------------------------------------------------------------
+// GetRegisterDstCount: Get the number of registers defined by the node.
+//
+// Arguments:
+//    None
+//
+// Return Value:
+//    The number of registers that this node defines.
+//
+// Notes:
+//    This should not be called on a contained node.
+//    This does not look at the actual register assignments, if any, and so
+//    is valid after Lowering.
+//
+int GenTree::GetRegisterDstCount() const
+{
+    assert(!isContained());
+    if (!IsMultiRegNode())
+    {
+        return (IsValue()) ? 1 : 0;
+    }
+    else if (IsMultiRegCall())
+    {
+        // temporarily cast away const-ness as AsCall() method is not declared const
+        GenTree* temp = const_cast<GenTree*>(this);
+        return temp->AsCall()->GetReturnTypeDesc()->GetReturnRegCount();
+    }
+    else if (IsCopyOrReloadOfMultiRegCall())
+    {
+        // A multi-reg copy or reload, will have valid regs for only those
+        // positions that need to be copied or reloaded.  Hence we need
+        // to consider only those registers for computing reg mask.
+
+        GenTree*             tree         = const_cast<GenTree*>(this);
+        GenTreeCopyOrReload* copyOrReload = tree->AsCopyOrReload();
+        GenTreeCall*         call         = copyOrReload->gtGetOp1()->AsCall();
+        return call->GetReturnTypeDesc()->GetReturnRegCount();
+    }
+#if !defined(LEGACY_BACKEND) && defined(_TARGET_ARM_)
+    else if (OperIsPutArgSplit())
+    {
+        return (const_cast<GenTree*>(this))->AsPutArgSplit()->gtNumRegs;
+    }
+    // A PUTARG_REG could be a MultiRegOp on ARM since we could move a double register to two int registers,
+    // either for all double parameters w/SoftFP or for varargs).
+    else
+    {
+        assert(OperIsMultiRegOp());
+        return (TypeGet() == TYP_LONG) ? 2 : 1;
+    }
+#endif // !defined(LEGACY_BACKEND) && defined(_TARGET_ARM_)
+    assert(!"Unexpected multi-reg node");
+    return 0;
+}
+
 //---------------------------------------------------------------
 // gtGetRegMask: Get the reg mask of the node.
 //
@@ -16065,19 +16120,6 @@ bool Compiler::gtComplexityExceeds(GenTreePtr* tree, unsigned limit)
     }
 }
 
-// -------------------------------------------------------------------------
-// IsRegOptional: Returns true if this gentree node is marked by lowering to
-// indicate that codegen can still generate code even if it wasn't allocated
-// a register.
-bool GenTree::IsRegOptional() const
-{
-#ifdef LEGACY_BACKEND
-    return false;
-#else
-    return gtLsraInfo.regOptional;
-#endif
-}
-
 bool GenTree::IsPhiNode()
 {
     return (OperGet() == GT_PHI_ARG) || (OperGet() == GT_PHI) || IsPhiDefn();

src/jit/gentree.h

@@ -680,6 +680,8 @@ struct GenTree
     void CopyReg(GenTreePtr from);
     bool gtHasReg() const;
 
+    int GetRegisterDstCount() const;
+
     regMaskTP gtGetRegMask() const;
 
     unsigned gtFlags; // see GTF_xxxx below
@@ -702,10 +704,6 @@ struct GenTree
     regMaskSmall gtUsedRegs; // set of used (trashed) registers
 #endif                       // LEGACY_BACKEND
 
-#ifndef LEGACY_BACKEND
-    TreeNodeInfo gtLsraInfo;
-#endif // !LEGACY_BACKEND
-
     void SetVNsFromNode(GenTreePtr tree)
     {
         gtVNPair = tree->gtVNPair;
@@ -1022,8 +1020,9 @@ struct GenTree
 #define GTF_DEBUG_NODE_LARGE        0x00000004
 #define GTF_DEBUG_NODE_CG_PRODUCED  0x00000008 // genProduceReg has been called on this node
 #define GTF_DEBUG_NODE_CG_CONSUMED  0x00000010 // genConsumeReg has been called on this node
+#define GTF_DEBUG_NODE_LSRA_ADDED   0x00000020 // This node was added by LSRA
 
-#define GTF_DEBUG_NODE_MASK         0x0000001F // These flags are all node (rather than operation) properties.
+#define GTF_DEBUG_NODE_MASK         0x0000003F // These flags are all node (rather than operation) properties.
 
 #define GTF_DEBUG_VAR_CSE_REF       0x00800000 // GT_LCL_VAR -- This is a CSE LCL_VAR node
 #endif // defined(DEBUG)
@@ -1133,10 +1132,20 @@ struct GenTree
         }
     }
 
-    // NOTE: the three UnusedValue helpers immediately below are defined in lir.h.
+    // LIR flags
+    //   These helper methods, along with the flag values they manipulate, are defined in lir.h
+    //
+    // UnusedValue indicates that, although this node produces a value, it is unused.
     inline void SetUnusedValue();
     inline void ClearUnusedValue();
     inline bool IsUnusedValue() const;
+    // RegOptional indicates that codegen can still generate code even if it isn't allocated a register.
+    inline bool IsRegOptional() const;
+    inline void SetRegOptional();
+    inline void ClearRegOptional();
+#ifdef DEBUG
+    void dumpLIRFlags();
+#endif
 
     bool OperIs(genTreeOps oper) const
     {
@@ -2135,17 +2144,6 @@ struct GenTree
     inline var_types  CastFromType();
     inline var_types& CastToType();
 
-    // Returns true if this gentree node is marked by lowering to indicate
-    // that codegen can still generate code even if it wasn't allocated a
-    // register.
-    bool IsRegOptional() const;
-#ifndef LEGACY_BACKEND
-    void ClearRegOptional()
-    {
-        gtLsraInfo.regOptional = false;
-    }
-#endif
-
     // Returns "true" iff "this" is a phi-related node (i.e. a GT_PHI_ARG, GT_PHI, or a PhiDefn).
     bool IsPhiNode();
 

src/jit/lir.cpp

@@ -1763,3 +1763,10 @@ void LIR::InsertBeforeTerminator(BasicBlock* block, LIR::Range&& range)
 
     blockRange.InsertBefore(insertionPoint, std::move(range));
 }
+
+#ifdef DEBUG
+void GenTree::dumpLIRFlags()
+{
+    JITDUMP("[%c%c%c]", IsUnusedValue() ? 'U' : '-', IsRegOptional() ? 'O' : '-');
+}
+#endif

src/jit/lir.h

@@ -38,6 +38,9 @@ class LIR final
                                 // that this bit should not be assumed to be valid
                                 // at all points during compilation: it is currently
                                 // only computed during target-dependent lowering.
+
+            RegOptional = 0x04, // Set on a node if it produces a value, but does not
+                                // require a register (i.e. it can be used from memory).
         };
     };
 
@@ -327,4 +330,19 @@ inline bool GenTree::IsUnusedValue() const
     return (gtLIRFlags & LIR::Flags::UnusedValue) != 0;
 }
 
+inline void GenTree::SetRegOptional()
+{
+    gtLIRFlags |= LIR::Flags::RegOptional;
+}
+
+inline void GenTree::ClearRegOptional()
+{
+    gtLIRFlags &= ~LIR::Flags::RegOptional;
+}
+
+inline bool GenTree::IsRegOptional() const
+{
+    return (gtLIRFlags & LIR::Flags::RegOptional) != 0;
+}
+
 #endif // _LIR_H_

src/jit/lower.cpp

@@ -4747,19 +4747,19 @@ bool Lowering::LowerUnsignedDivOrMod(GenTreeOp* divMod)
 //    node - pointer to the DIV or MOD node
 //
 // Returns:
-//    The next node to lower.
+//    nullptr if no transformation is done, or the next node in the transformed node sequence that
+//    needs to be lowered.
 //
 GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
 {
     assert((node->OperGet() == GT_DIV) || (node->OperGet() == GT_MOD));
-    GenTree* next     = node->gtNext;
     GenTree* divMod   = node;
     GenTree* dividend = divMod->gtGetOp1();
     GenTree* divisor  = divMod->gtGetOp2();
 
     if (!divisor->IsCnsIntOrI())
     {
-        return next; // no transformations to make
+        return nullptr; // no transformations to make
     }
 
     const var_types type = divMod->TypeGet();
@@ -4770,7 +4770,7 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
         // We shouldn't see a divmod with constant operands here but if we do then it's likely
         // because optimizations are disabled or it's a case that's supposed to throw an exception.
         // Don't optimize this.
-        return next;
+        return nullptr;
     }
 
     ssize_t divisorValue = divisor->gtIntCon.IconValue();
@@ -4786,7 +4786,7 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
         // case so optimizing this case would break C# code.
 
         // A runtime check could be used to handle this case but it's probably too rare to matter.
-        return next;
+        return nullptr;
     }
 
     bool isDiv = divMod->OperGet() == GT_DIV;
@@ -4798,8 +4798,7 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
             // If the divisor is the minimum representable integer value then we can use a compare,
             // the result is 1 iff the dividend equals divisor.
             divMod->SetOper(GT_EQ);
-            ContainCheckCompare(divMod->AsOp());
-            return next;
+            return node;
         }
     }
 
@@ -4810,7 +4809,7 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
     {
         if (comp->opts.MinOpts())
         {
-            return next;
+            return nullptr;
         }
 
 #if defined(_TARGET_XARCH_) || defined(_TARGET_ARM64_)
@@ -4921,15 +4920,15 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
         return mulhi;
 #else
         // Currently there's no GT_MULHI for ARM32
-        return next;
+        return nullptr;
 #endif
     }
 
     // We're committed to the conversion now. Go find the use if any.
     LIR::Use use;
     if (!BlockRange().TryGetUse(node, &use))
     {
-        return next;
+        return nullptr;
     }
 
     // We need to use the dividend node multiple times so its value needs to be
@@ -5030,13 +5029,14 @@ GenTree* Lowering::LowerSignedDivOrMod(GenTreePtr node)
     if (!varTypeIsFloating(node->TypeGet()))
 #endif // _TARGET_XARCH_
     {
-        next = LowerConstIntDivOrMod(node);
-    }
-
-    if ((node->OperGet() == GT_DIV) || (node->OperGet() == GT_MOD))
-    {
-        ContainCheckDivOrMod(node->AsOp());
+        // LowerConstIntDivOrMod will return nullptr if it doesn't transform the node.
+        GenTree* newNode = LowerConstIntDivOrMod(node);
+        if (newNode != nullptr)
+        {
+            return newNode;
+        }
     }
+    ContainCheckDivOrMod(node->AsOp());
 
     return next;
 }
@@ -5890,7 +5890,7 @@ void Lowering::ContainCheckDivOrMod(GenTreeOp* node)
         {
             // If there are no containable operands, we can make an operand reg optional.
             // SSE2 allows only divisor to be a memory-op.
-            SetRegOptional(divisor);
+            divisor->SetRegOptional();
         }
         return;
     }
@@ -5912,7 +5912,7 @@ void Lowering::ContainCheckDivOrMod(GenTreeOp* node)
     {
         // If there are no containable operands, we can make an operand reg optional.
         // Div instruction allows only divisor to be a memory op.
-        SetRegOptional(divisor);
+        divisor->SetRegOptional();
     }
 #endif // _TARGET_XARCH_
 }

src/jit/lower.h

@@ -224,22 +224,6 @@ class Lowering : public Phase
     bool IsCallTargetInRange(void* addr);
 
 #if defined(_TARGET_XARCH_)
-    //----------------------------------------------------------------------
-    // SetRegOptional - sets a bit to indicate to LSRA that register
-    // for a given tree node is optional for codegen purpose.  If no
-    // register is allocated to such a tree node, its parent node treats
-    // it as a contained memory operand during codegen.
-    //
-    // Arguments:
-    //    tree    -   GenTree node
-    //
-    // Returns
-    //    None
-    void SetRegOptional(GenTree* tree)
-    {
-        tree->gtLsraInfo.regOptional = true;
-    }
-
     GenTree* PreferredRegOptionalOperand(GenTree* tree);
 
     // ------------------------------------------------------------------
@@ -273,13 +257,18 @@ class Lowering : public Phase
         const bool op1Legal = tree->OperIsCommutative() && (operatorSize == genTypeSize(op1->TypeGet()));
         const bool op2Legal = operatorSize == genTypeSize(op2->TypeGet());
 
+        GenTree* regOptionalOperand = nullptr;
         if (op1Legal)
         {
-            SetRegOptional(op2Legal ? PreferredRegOptionalOperand(tree) : op1);
+            regOptionalOperand = op2Legal ? PreferredRegOptionalOperand(tree) : op1;
         }
         else if (op2Legal)
         {
-            SetRegOptional(op2);
+            regOptionalOperand = op2;
+        }
+        if (regOptionalOperand != nullptr)
+        {
+            regOptionalOperand->SetRegOptional();
         }
     }
 #endif // defined(_TARGET_XARCH_)