Skip to content
This repository was archived by the owner on Jan 23, 2023. It is now read-only.

Commit 592aa82

Browse files
tannergoodingtannergooding
committed
Fixing the hwintrin codgen containment checks
1 parent 6804e99 commit 592aa82

File tree

3 files changed

+37
-73
lines changed

3 files changed

+37
-73
lines changed

‎src/jit/emitxarch.cpp‎

Lines changed: 16 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -3891,18 +3891,15 @@ void emitter::emitIns_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regN
38913891
emitCurIGsize += sz;
38923892
}
38933893

3894-
void emitter::emitIns_R_A(
3895-
instruction ins, emitAttr attr, regNumber reg1, regNumber baseReg, regNumber indxReg, size_t scale, ssize_t offs)
3894+
void emitter::emitIns_R_A(instruction ins, emitAttr attr, regNumber reg1, GenTreeIndir* indir, insFormat fmt)
38963895
{
3897-
instrDesc* id = emitNewInstrAmd(attr, offs);
3896+
ssize_t offs = indir->Offset();
3897+
instrDesc* id = emitNewInstrAmd(attr, offs);
3898+
38983899
id->idIns(ins);
3899-
id->idInsFmt(IF_RRW_ARD);
39003900
id->idReg1(reg1);
3901-
id->idAddr()->iiaAddrMode.amBaseReg = baseReg;
3902-
id->idAddr()->iiaAddrMode.amIndxReg = indxReg;
3903-
id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(scale);
39043901

3905-
assert(emitGetInsAmdAny(id) == offs);
3902+
emitHandleMemOp(indir, id, fmt, ins);
39063903

39073904
UNATIVE_OFFSET sz = emitInsSizeAM(id, insCodeRM(ins));
39083905
id->idCodeSize(sz);
@@ -3911,32 +3908,24 @@ void emitter::emitIns_R_A(
39113908
emitCurIGsize += sz;
39123909
}
39133910

3914-
void emitter::emitIns_R_R_A(instruction ins,
3915-
emitAttr attr,
3916-
regNumber reg1,
3917-
regNumber reg2,
3918-
regNumber baseReg,
3919-
regNumber indxReg,
3920-
size_t scale,
3921-
ssize_t offs)
3911+
void emitter::emitIns_R_R_A(
3912+
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, GenTreeIndir* indir, insFormat fmt)
39223913
{
39233914
assert(IsSSEOrAVXInstruction(ins));
39243915
assert(IsThreeOperandAVXInstruction(ins));
39253916

3926-
instrDesc* id = emitNewInstrAmd(attr, offs);
3927-
UNATIVE_OFFSET sz = emitInsSizeAM(id, insCodeRM(ins)) + emitGetVexPrefixAdjustedSize(ins, attr, insCodeRM(ins));
3917+
ssize_t offs = indir->Offset();
3918+
instrDesc* id = emitNewInstrAmd(attr, offs);
39283919

39293920
id->idIns(ins);
3930-
id->idInsFmt(IF_RWR_RRD_ARD);
39313921
id->idReg1(reg1);
39323922
id->idReg2(reg2);
3933-
id->idAddr()->iiaAddrMode.amBaseReg = baseReg;
3934-
id->idAddr()->iiaAddrMode.amIndxReg = indxReg;
3935-
id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(scale);
39363923

3937-
assert(emitGetInsAmdAny(id) == offs);
3924+
emitHandleMemOp(indir, id, fmt, ins);
39383925

3926+
UNATIVE_OFFSET sz = emitInsSizeAM(id, insCodeRM(ins)) + emitGetVexPrefixAdjustedSize(ins, attr, insCodeRM(ins));
39393927
id->idCodeSize(sz);
3928+
39403929
dispIns(id);
39413930
emitCurIGsize += sz;
39423931
}
@@ -4990,26 +4979,20 @@ void emitter::emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNu
49904979
}
49914980

49924981
#if FEATURE_HW_INTRINSICS
4993-
void emitter::emitIns_SIMD_R_R_A(instruction ins,
4994-
regNumber reg,
4995-
regNumber reg1,
4996-
regNumber baseReg,
4997-
regNumber indxReg,
4998-
size_t scale,
4999-
ssize_t offs,
5000-
var_types simdtype)
4982+
void emitter::emitIns_SIMD_R_R_A(
4983+
instruction ins, regNumber reg, regNumber reg1, GenTreeIndir* indir, var_types simdtype)
50014984
{
50024985
if (UseVEXEncoding())
50034986
{
5004-
emitIns_R_R_A(ins, emitTypeSize(simdtype), reg, reg1, baseReg, indxReg, scale, offs);
4987+
emitIns_R_R_A(ins, emitTypeSize(simdtype), reg, reg1, indir, IF_RWR_RRD_ARD);
50054988
}
50064989
else
50074990
{
50084991
if (reg1 != reg)
50094992
{
50104993
emitIns_R_R(INS_movaps, emitTypeSize(simdtype), reg, reg1);
50114994
}
5012-
emitIns_R_A(ins, emitTypeSize(simdtype), reg, baseReg, indxReg, scale, offs);
4995+
emitIns_R_A(ins, emitTypeSize(simdtype), reg, indir, IF_RRW_ARD);
50134996
}
50144997
}
50154998

‎src/jit/emitxarch.h‎

Lines changed: 4 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -365,17 +365,9 @@ void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2)
365365

366366
void emitIns_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int ival);
367367

368-
void emitIns_R_A(
369-
instruction ins, emitAttr attr, regNumber reg1, regNumber baseReg, regNumber indxReg, size_t scale, ssize_t offs);
370-
371-
void emitIns_R_R_A(instruction ins,
372-
emitAttr attr,
373-
regNumber reg1,
374-
regNumber reg2,
375-
regNumber baseReg,
376-
regNumber indxReg,
377-
size_t scale,
378-
ssize_t offs);
368+
void emitIns_R_A(instruction ins, emitAttr attr, regNumber reg1, GenTreeIndir* indir, insFormat fmt);
369+
370+
void emitIns_R_R_A(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, GenTreeIndir* indir, insFormat fmt);
379371

380372
void emitIns_R_R_C(
381373
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, CORINFO_FIELD_HANDLE fldHnd, int offs);
@@ -441,14 +433,7 @@ void emitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg,
441433
void emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp);
442434

443435
#if FEATURE_HW_INTRINSICS
444-
void emitIns_SIMD_R_R_A(instruction ins,
445-
regNumber reg,
446-
regNumber reg1,
447-
regNumber baseReg,
448-
regNumber indxReg,
449-
size_t scale,
450-
ssize_t offs,
451-
var_types simdtype);
436+
void emitIns_SIMD_R_R_A(instruction ins, regNumber reg, regNumber reg1, GenTreeIndir* indir, var_types simdtype);
452437
void emitIns_SIMD_R_R_C(
453438
instruction ins, regNumber reg, regNumber reg1, CORINFO_FIELD_HANDLE fldHnd, int offs, var_types simdtype);
454439
void emitIns_SIMD_R_R_R(instruction ins, regNumber reg, regNumber reg1, regNumber reg2, var_types simdtype);

‎src/jit/hwintrinsiccodegenxarch.cpp‎

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,20 @@ void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins)
105105
unsigned varNum = BAD_VAR_NUM;
106106
unsigned offset = (unsigned)-1;
107107

108-
if (op2->isIndir())
108+
if (op2->isUsedFromSpillTemp())
109109
{
110-
assert(op2->isContained());
110+
assert(op2->IsRegOptional());
111111

112-
GenTreeIndir* mem = op2->AsIndir();
113-
GenTree* memBase = mem->Base();
112+
tmpDsc = getSpillTempDsc(op2);
113+
varNum = tmpDsc->tdTempNum();
114+
offset = 0;
115+
116+
compiler->tmpRlsTemp(tmpDsc);
117+
}
118+
else if (op2->isIndir())
119+
{
120+
GenTreeIndir* memIndir = op2->AsIndir();
121+
GenTree* memBase = memIndir->gtOp1;
114122

115123
switch (memBase->OperGet())
116124
{
@@ -121,9 +129,9 @@ void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins)
121129

122130
// Ensure that all the GenTreeIndir values are set to their defaults.
123131
assert(memBase->gtRegNum == REG_NA);
124-
assert(!mem->HasIndex());
125-
assert(mem->Scale() == 1);
126-
assert(mem->Offset() == 0);
132+
assert(!memIndir->HasIndex());
133+
assert(memIndir->Scale() == 1);
134+
assert(memIndir->Offset() == 0);
127135

128136
break;
129137
}
@@ -136,9 +144,7 @@ void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins)
136144

137145
default:
138146
{
139-
regNumber indxReg = mem->HasIndex() ? mem->Index()->gtRegNum : REG_NA;
140-
emit->emitIns_SIMD_R_R_A(ins, targetReg, op1Reg, memBase->gtRegNum, indxReg, mem->Scale(),
141-
mem->Offset(), targetType);
147+
emit->emitIns_SIMD_R_R_A(ins, targetReg, op1Reg, memIndir, targetType);
142148
return;
143149
}
144150
}
@@ -159,24 +165,14 @@ void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins)
159165
case GT_LCL_VAR:
160166
{
161167
assert(op2->IsRegOptional() || !compiler->lvaTable[op2->gtLclVar.gtLclNum].lvIsRegCandidate());
162-
163168
varNum = op2->AsLclVar()->GetLclNum();
164169
offset = 0;
165170
break;
166171
}
167172

168173
default:
169-
{
170-
assert(op2->isUsedFromSpillTemp());
171-
assert(op2->IsRegOptional());
172-
173-
tmpDsc = getSpillTempDsc(op2);
174-
varNum = tmpDsc->tdTempNum();
175-
offset = 0;
176-
177-
compiler->tmpRlsTemp(tmpDsc);
174+
unreached();
178175
break;
179-
}
180176
}
181177
}
182178

0 commit comments

Comments
 (0)