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Fix informations in Userspace/Handling_Interrupts #115

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Merged
merged 2 commits into from
May 31, 2025
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Fix informations in Userspace/Handling_Interrupts #115

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550c8f9
fix informations in tss struct and layout of tss system descriptor
AntoninRuan May 24, 2025
aef7c69
add AntoninRuan in acknowledgments
AntoninRuan May 30, 2025
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7 changes: 3 additions & 4 deletions 06_Userspace/03_Handling_Interrupts.md
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Expand Up @@ -22,16 +22,15 @@ typedef struct tss
uint64_t rsp1;
uint64_t rsp2;
uint64_t reserved1;
uint64_t reserved2;
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@dreamos82 dreamos82 May 25, 2025

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I'm wondering, could be more readable to keep reserved1 and reserverd2 changing the size, instead of deleting one? To just try to keep it similar to the image (although i know that even the IST fields are represented as two 32bits chunks).
What do you think? (@DeanoBurrito any input from you? )

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@AntoninRuan AntoninRuan May 25, 2025

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Yeah I was wondering what was the "better" solution. I chose to remove a field rather than changing the size, as in my mind the less "useless" / reserved field the better. Also given all the other fields are already uint64_t having the reserved one as well can remove doubt about a typo I think, but still very subjective

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@DeanoBurrito DeanoBurrito May 26, 2025

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I agree it's definitely subjective, for me I think the single (albeit misaligned) uint64_t is the best way in terms of readability.

uint64_t ist1;
uint64_t ist2;
uint64_t ist3;
uint64_t ist4;
uint64_t ist5;
uint64_t ist6;
uint64_t ist7;
uint64_t reserved3;
uint16_t reserved4;
uint64_t reserved2;
uint16_t reserved3;
uint16_t io_bitmap_offset;
}__attribute__((__packed__)) tss_t;
```
Expand Down Expand Up @@ -60,7 +59,7 @@ The layout of the TSS system descriptor is broken down below in the following ta
| 39:32 | TSS address bits 23:16 | Contains the next 8 bits of the tss address. |
| 47:40 | 0b10001001 | Sets the type of GDT descriptor, its DPL (bits 45:46) to 0, marks it as present (bit 47). Bit 44 (S) along with bits 40 to 43 indicate the type of descriptor. If curious as to how this value was created, see the intel SDM manual or our section about the GDT.|
| 48:51 | Limit 16:9 | The higher part of the limit field, bits 9 to 16 |
| 55:52 | 0bG000A | Additional fields for the TSS entry. Where G (bit 55) is the granularity bit and A (bit 52) is a bit left available to the operating system. The other bits must be left as 0 |
| 55:52 | 0bG00A | Additional fields for the TSS entry. Where G (bit 55) is the granularity bit and A (bit 52) is a bit left available to the operating system. The other bits must be left as 0 |
| 63:56 | TSS address bits 31:24 | Contains the next 8 bits of the tss address. |
| 95:64 | TSS address bits 63:32 | Contains the upper 32 bits of the tss address. |
| 96:127 | Reserved | They should be left as 0. |
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1 change: 1 addition & 0 deletions 99_Appendices/I_Acknowledgments.md
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Expand Up @@ -24,3 +24,4 @@ In no particular order:
- @mrjbom ([https://github.com/mrjbom](https://github.com/mrjbom))
- @IAmTheNerdNextDoor ([https://github.com/IAmTheNerdNextDoor](https://github.com/IAmTheNerdNextDoor))
- @vasilisalmpanis ([https://github.com/vasilisalmpanis](https://github.com/vasilisalmpanis))
- @AntoninRuan ([https://github.com/AntoninRuan](https://github.com/AntoninRuan))