feat(esp32c61): Add support for ESP32-C61

.github/scripts/find_all_boards.sh

@@ -8,7 +8,7 @@ boards_list=$(grep '.tarch=' boards.txt)
 while read -r line; do
     board_name=$(echo "$line" | cut -d '.' -f1 | cut -d '#' -f1)
     # skip esp32c2 as we dont build libs for it
-    if [ "$board_name" == "esp32c2" ]; then
+    if [ "$board_name" == "esp32c2" ] || [ "$board_name" == "esp32c61" ]; then
         echo "Skipping 'espressif:esp32:$board_name'"
         continue
     fi

.github/workflows/build_component.yml

@@ -4,13 +4,13 @@ on:
   workflow_dispatch:
     inputs:
       idf_ver:
-        description: "IDF Versions"
-        default: "release-v5.3,release-v5.4,release-v5.5"
+        description: "Comma separated list of IDF branches to build"
+        default: "release-v5.5"
         type: "string"
         required: true
       idf_targets:
-        description: "IDF Targets"
-        default: "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2,esp32p4"
+        description: "Comma separated list of IDF targets to build"
+        default: "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4"
         type: "string"
         required: false
   push:
@@ -37,6 +37,7 @@ on:
       - "variants/esp32c3/**"
       - "variants/esp32c5/**"
       - "variants/esp32c6/**"
+      - "variants/esp32c61/**"
       - "variants/esp32h2/**"
       - "variants/esp32p4/**"
       - "variants/esp32s2/**"
@@ -125,7 +126,7 @@ jobs:
                 echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2,esp32p4"
                 ;;
               "release-v5.5")
-                echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32h2,esp32p4"
+                echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4"
                 ;;
               *)
                 echo ""

CMakeLists.txt

@@ -378,7 +378,7 @@ set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hi
 if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread)
   #if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work!
   #if(CONFIG_OPENTHREAD_ENABLED) # Does not work!
-  if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5") # Sadly only this works
+  if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5" OR IDF_TARGET STREQUAL "esp32c61") # Sadly only this works
     list(APPEND requires openthread)
   endif()
 endif()

README.md

@@ -76,7 +76,7 @@ Here are the ESP32 series supported by the Arduino-ESP32 project:
 | ESP32-S3 |     Yes    |       Yes       | [ESP32-S3](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) |
 
 > [!NOTE]
-> ESP32-C2 is also supported by Arduino-ESP32 but requires using Arduino as an ESP-IDF component or rebuilding the static libraries.
+> ESP32-C2 and ESP32-C61 are also supported by Arduino-ESP32 but require using Arduino as an ESP-IDF component or rebuilding the static libraries.
 > For more information, see the [Arduino as an ESP-IDF component documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/esp-idf_component.html) or the
 > [Lib Builder documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/lib_builder.html), respectively.
 

boards.txt

@@ -983,6 +983,176 @@ esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lz
 
 ##############################################################
 
+esp32c61.name=ESP32C61 Dev Module
+esp32c61.hide=true
+
+esp32c61.bootloader.tool=esptool_py
+esp32c61.bootloader.tool.default=esptool_py
+
+esp32c61.upload.tool=esptool_py
+esp32c61.upload.tool.default=esptool_py
+esp32c61.upload.tool.network=esp_ota
+
+esp32c61.upload.maximum_size=1310720
+esp32c61.upload.maximum_data_size=327680
+esp32c61.upload.flags=
+esp32c61.upload.extra_flags=
+esp32c61.upload.use_1200bps_touch=false
+esp32c61.upload.wait_for_upload_port=false
+
+esp32c61.serial.disableDTR=false
+esp32c61.serial.disableRTS=false
+
+esp32c61.build.tarch=riscv32
+esp32c61.build.target=esp
+esp32c61.build.mcu=esp32c61
+esp32c61.build.core=esp32
+esp32c61.build.variant=esp32c61
+esp32c61.build.board=ESP32C61_DEV
+esp32c61.build.bootloader_addr=0x0
+
+esp32c61.build.cdc_on_boot=0
+esp32c61.build.f_cpu=160000000L
+esp32c61.build.flash_size=4MB
+esp32c61.build.flash_freq=80m
+esp32c61.build.flash_mode=qio
+esp32c61.build.boot=qio
+esp32c61.build.partitions=default
+esp32c61.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c61.menu.JTAGAdapter.default=Disabled
+esp32c61.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c61.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c61.menu.JTAGAdapter.builtin.build.openocdscript=esp32c61-builtin.cfg
+esp32c61.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c61.menu.JTAGAdapter.external=FTDI Adapter
+esp32c61.menu.JTAGAdapter.external.build.openocdscript=esp32c61-ftdi.cfg
+esp32c61.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c61.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c61.menu.JTAGAdapter.bridge.build.openocdscript=esp32c61-bridge.cfg
+esp32c61.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c61.menu.PSRAM.disabled=Disabled
+esp32c61.menu.PSRAM.disabled.build.defines=
+esp32c61.menu.PSRAM.enabled=Enabled
+esp32c61.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32c61.menu.CDCOnBoot.default=Disabled
+esp32c61.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c61.menu.CDCOnBoot.cdc=Enabled
+esp32c61.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c61.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c61.menu.PartitionScheme.default.build.partitions=default
+esp32c61.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c61.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c61.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c61.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c61.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c61.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c61.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c61.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32c61.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32c61.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32c61.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c61.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c61.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c61.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c61.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c61.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c61.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c61.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c61.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c61.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c61.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c61.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c61.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c61.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c61.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c61.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c61.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c61.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c61.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c61.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c61.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c61.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c61.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c61.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c61.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c61.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c61.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000
+esp32c61.menu.PartitionScheme.custom=Custom
+esp32c61.menu.PartitionScheme.custom.build.partitions=
+esp32c61.menu.PartitionScheme.custom.upload.maximum_size=8388608
+
+esp32c61.menu.CPUFreq.160=160MHz (WiFi)
+esp32c61.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c61.menu.CPUFreq.120=120MHz (WiFi)
+esp32c61.menu.CPUFreq.120.build.f_cpu=120000000L
+esp32c61.menu.CPUFreq.80=80MHz (WiFi)
+esp32c61.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c61.menu.CPUFreq.40=40MHz
+esp32c61.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c61.menu.CPUFreq.20=20MHz
+esp32c61.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c61.menu.CPUFreq.10=10MHz
+esp32c61.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c61.menu.FlashMode.qio=QIO
+esp32c61.menu.FlashMode.qio.build.flash_mode=dio
+esp32c61.menu.FlashMode.qio.build.boot=qio
+esp32c61.menu.FlashMode.dio=DIO
+esp32c61.menu.FlashMode.dio.build.flash_mode=dio
+esp32c61.menu.FlashMode.dio.build.boot=dio
+
+esp32c61.menu.FlashFreq.80=80MHz
+esp32c61.menu.FlashFreq.80.build.flash_freq=80m
+esp32c61.menu.FlashFreq.40=40MHz
+esp32c61.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c61.menu.FlashSize.4M=4MB (32Mb)
+esp32c61.menu.FlashSize.4M.build.flash_size=4MB
+esp32c61.menu.FlashSize.8M=8MB (64Mb)
+esp32c61.menu.FlashSize.8M.build.flash_size=8MB
+esp32c61.menu.FlashSize.2M=2MB (16Mb)
+esp32c61.menu.FlashSize.2M.build.flash_size=2MB
+
+esp32c61.menu.UploadSpeed.921600=921600
+esp32c61.menu.UploadSpeed.921600.upload.speed=921600
+esp32c61.menu.UploadSpeed.115200=115200
+esp32c61.menu.UploadSpeed.115200.upload.speed=115200
+esp32c61.menu.UploadSpeed.256000.windows=256000
+esp32c61.menu.UploadSpeed.256000.upload.speed=256000
+esp32c61.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c61.menu.UploadSpeed.230400=230400
+esp32c61.menu.UploadSpeed.230400.upload.speed=230400
+esp32c61.menu.UploadSpeed.460800.linux=460800
+esp32c61.menu.UploadSpeed.460800.macosx=460800
+esp32c61.menu.UploadSpeed.460800.upload.speed=460800
+esp32c61.menu.UploadSpeed.512000.windows=512000
+esp32c61.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c61.menu.DebugLevel.none=None
+esp32c61.menu.DebugLevel.none.build.code_debug=0
+esp32c61.menu.DebugLevel.error=Error
+esp32c61.menu.DebugLevel.error.build.code_debug=1
+esp32c61.menu.DebugLevel.warn=Warn
+esp32c61.menu.DebugLevel.warn.build.code_debug=2
+esp32c61.menu.DebugLevel.info=Info
+esp32c61.menu.DebugLevel.info.build.code_debug=3
+esp32c61.menu.DebugLevel.debug=Debug
+esp32c61.menu.DebugLevel.debug.build.code_debug=4
+esp32c61.menu.DebugLevel.verbose=Verbose
+esp32c61.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c61.menu.EraseFlash.none=Disabled
+esp32c61.menu.EraseFlash.none.upload.erase_cmd=
+esp32c61.menu.EraseFlash.all=Enabled
+esp32c61.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
 esp32s3.name=ESP32S3 Dev Module
 
 esp32s3.bootloader.tool=esptool_py

cores/esp32/Esp.cpp

@@ -83,6 +83,9 @@ extern "C" {
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/spi_flash.h"
 #define ESP_FLASH_IMAGE_BASE 0x2000  // Esp32c5 is located at 0x2000
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32c61 is located at 0x0000
 #else
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -365,7 +368,7 @@ uint32_t EspClass::getFlashChipSpeed(void) {
 }
 
 FlashMode_t EspClass::getFlashChipMode(void) {
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
   uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
 #elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
   uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
@@ -449,6 +452,22 @@ uint32_t EspClass::magicFlashChipSpeed(uint8_t flashByte) {
       return 0;
   }
 
+#elif CONFIG_IDF_TARGET_ESP32C61
+  /*
+    FLASH_FREQUENCY = {
+        "80m": 0xF,
+        "40m": 0x0,
+        "20m": 0x2,
+    }
+*/
+  switch (flashByte & 0x0F) {
+    case 0xF: return (80_MHz);
+    case 0x0: return (40_MHz);
+    case 0x2: return (20_MHz);
+    default:  // fail?
+      return 0;
+  }
+
 #elif CONFIG_IDF_TARGET_ESP32H2
 
   /*

cores/esp32/HardwareSerial.h

@@ -164,6 +164,8 @@ typedef enum {
 #define SOC_RX0 (gpio_num_t)38
 #elif CONFIG_IDF_TARGET_ESP32C5
 #define SOC_RX0 (gpio_num_t)12
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define SOC_RX0 (gpio_num_t)10
 #endif
 #endif
 
@@ -182,7 +184,7 @@ typedef enum {
 #define SOC_TX0 (gpio_num_t)24
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define SOC_TX0 (gpio_num_t)37
-#elif CONFIG_IDF_TARGET_ESP32C5
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 #define SOC_TX0 (gpio_num_t)11
 #endif
 #endif
@@ -209,6 +211,8 @@ typedef enum {
 #define RX1 (gpio_num_t)11
 #elif CONFIG_IDF_TARGET_ESP32C5
 #define RX1 (gpio_num_t)4
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define RX1 (gpio_num_t)8
 #endif
 #endif
 
@@ -231,6 +235,8 @@ typedef enum {
 #define TX1 (gpio_num_t)10
 #elif CONFIG_IDF_TARGET_ESP32C5
 #define TX1 (gpio_num_t)5
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define TX1 (gpio_num_t)29
 #endif
 #endif
 #endif /* SOC_UART_HP_NUM > 1 */

cores/esp32/chip-debug-report.cpp

@@ -69,9 +69,8 @@ static void printPkgVersion(void) {
 #elif CONFIG_IDF_TARGET_ESP32P4
   uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION);
   chip_report_printf("%lu", pkg_ver);
-#elif CONFIG_IDF_TARGET_ESP32C5
-  // ToDo: Update this line when EFUSE_PKG_VERSION is available again for ESP32-C5
-  uint32_t pkg_ver = 0;  //REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION);
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION);
   chip_report_printf("%lu", pkg_ver);
 #else
   chip_report_printf("Unknown");