Add RISC-V support.

This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

Author: timsifive

doc/openocd.texi

@@ -8946,6 +8946,84 @@ Display all registers in @emph{group}.
  "timer" or any new group created with addreg command.
 @end deffn
 
+@section RISC-V Architecture
+
+@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
+debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug
+Specification.
+
+@subsection RISC-V Terminology
+
+A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
+another hart, or may be a separate core.  RISC-V treats those the same, and
+OpenOCD exposes each hart as a separate core.
+
+@subsection RISC-V Debug Configuration Commands
+
+@deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]...
+Configure a list of inclusive ranges for CSRs to expose in addition to the
+standard ones. This must be executed before `init`.
+
+By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
+and then only if the corresponding extension appears to be implemented. This
+command can be used if OpenOCD gets this wrong, or a target implements custom
+CSRs.
+@end deffn
+
+@deffn Command {riscv set_command_timeout_sec} [seconds]
+Set the wall-clock timeout (in seconds) for individual commands. The default
+should work fine for all but the slowest targets (eg. simulators).
+@end deffn
+
+@deffn Command {riscv set_reset_timeout_sec} [seconds]
+Set the maximum time to wait for a hart to come out of reset after reset is
+deasserted.
+@end deffn
+
+@deffn Command {riscv set_scratch_ram} none|[address]
+Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
+This is used to access 64-bit floating point registers on 32-bit targets.
+@end deffn
+
+@deffn Command {riscv set_prefer_sba} on|off
+When on, prefer to use System Bus Access to access memory.  When off, prefer to
+use the Program Buffer to access memory.
+@end deffn
+
+@subsection RISC-V Authentication Commands
+
+The following commands can be used to authenticate to a RISC-V system. Eg.  a
+trivial challenge-response protocol could be implemented as follows in a
+configuration file, immediately following @command{init}:
+@example
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+@end example
+
+@deffn Command {riscv authdata_read}
+Return the 32-bit value read from authdata. Note that to get read value back in
+a TCL script, it needs to be invoked as @command{ocd_riscv authdata_read}.
+@end deffn
+
+@deffn Command {riscv authdata_write} value
+Write the 32-bit value to authdata.
+@end deffn
+
+@subsection RISC-V DMI Commands
+
+The following commands allow direct access to the Debug Module Interface, which
+can be used to interact with custom debug features.
+
+@deffn Command {riscv dmi_read}
+Perform a 32-bit DMI read at address, returning the value.  Note that to get
+read value back in a TCL script, it needs to be invoked as @command{ocd_riscv
+dmi_read}.
+@end deffn
+
+@deffn Command {riscv dmi_write} address value
+Perform a 32-bit DMI write of value at address.
+@end deffn
+
 @anchor{softwaredebugmessagesandtracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support

src/helper/log.h

@@ -149,6 +149,8 @@ extern int debug_level;
  */
 #define ERROR_FAIL						(-4)
 #define ERROR_WAIT						(-5)
+/* ERROR_TIMEOUT is already taken by winerror.h. */
+#define ERROR_TIMEOUT_REACHED			(-6)
 
 
 #endif /* OPENOCD_HELPER_LOG_H */

src/target/Makefile.am

@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+	%D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -218,3 +220,4 @@ INTEL_IA32_SRC = \
 	%D%/arm_cti.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am

src/target/riscv/Makefile.am

@@ -0,0 +1,16 @@
+noinst_LTLIBRARIES += %D%/libriscv.la
+%C%_libriscv_la_SOURCES = \
+       %D%/asm.h \
+       %D%/batch.h \
+       %D%/debug_defines.h \
+       %D%/encoding.h \
+       %D%/gdb_regs.h \
+       %D%/opcodes.h \
+       %D%/program.h \
+       %D%/riscv.h \
+       %D%/batch.c \
+       %D%/program.c \
+       %D%/riscv-011.c \
+       %D%/riscv-013.c \
+       %D%/riscv.c \
+       %D%/riscv_semihosting.c

src/target/riscv/asm.h

@@ -0,0 +1,38 @@
+#ifndef TARGET__RISCV__ASM_H
+#define TARGET__RISCV__ASM_H
+
+#include "riscv.h"
+
+/*** Version-independent functions that we don't want in the main address space. ***/
+
+static uint32_t load(const struct target *target, unsigned int rd,
+		unsigned int base, uint16_t offset) __attribute__ ((unused));
+static uint32_t load(const struct target *target, unsigned int rd,
+		unsigned int base, uint16_t offset)
+{
+	switch (riscv_xlen(target)) {
+		case 32:
+			return lw(rd, base, offset);
+		case 64:
+			return ld(rd, base, offset);
+	}
+	assert(0);
+	return 0; /* Silence -Werror=return-type */
+}
+
+static uint32_t store(const struct target *target, unsigned int src,
+		unsigned int base, uint16_t offset) __attribute__ ((unused));
+static uint32_t store(const struct target *target, unsigned int src,
+		unsigned int base, uint16_t offset)
+{
+	switch (riscv_xlen(target)) {
+		case 32:
+			return sw(src, base, offset);
+		case 64:
+			return sd(src, base, offset);
+	}
+	assert(0);
+	return 0; /* Silence -Werror=return-type */
+}
+
+#endif

src/target/riscv/batch.c

@@ -0,0 +1,172 @@
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "batch.h"
+#include "debug_defines.h"
+#include "riscv.h"
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+static void dump_field(const struct scan_field *field);
+
+struct riscv_batch *riscv_batch_alloc(struct target *target, size_t scans, size_t idle)
+{
+	scans += 4;
+	struct riscv_batch *out = malloc(sizeof(*out));
+	memset(out, 0, sizeof(*out));
+	out->target = target;
+	out->allocated_scans = scans;
+	out->used_scans = 0;
+	out->idle_count = idle;
+	out->data_out = malloc(sizeof(*out->data_out) * (scans) * sizeof(uint64_t));
+	out->data_in  = malloc(sizeof(*out->data_in)  * (scans) * sizeof(uint64_t));
+	out->fields = malloc(sizeof(*out->fields) * (scans));
+	out->last_scan = RISCV_SCAN_TYPE_INVALID;
+	out->read_keys = malloc(sizeof(*out->read_keys) * (scans));
+	out->read_keys_used = 0;
+	return out;
+}
+
+void riscv_batch_free(struct riscv_batch *batch)
+{
+	free(batch->data_in);
+	free(batch->data_out);
+	free(batch->fields);
+	free(batch);
+}
+
+bool riscv_batch_full(struct riscv_batch *batch)
+{
+	return batch->used_scans > (batch->allocated_scans - 4);
+}
+
+int riscv_batch_run(struct riscv_batch *batch)
+{
+	if (batch->used_scans == 0) {
+		LOG_DEBUG("Ignoring empty batch.");
+		return ERROR_OK;
+	}
+
+	keep_alive();
+
+	LOG_DEBUG("running a batch of %ld scans", (long)batch->used_scans);
+	riscv_batch_add_nop(batch);
+
+	for (size_t i = 0; i < batch->used_scans; ++i) {
+		jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE);
+		if (batch->idle_count > 0)
+			jtag_add_runtest(batch->idle_count, TAP_IDLE);
+	}
+
+	LOG_DEBUG("executing queue");
+	if (jtag_execute_queue() != ERROR_OK) {
+		LOG_ERROR("Unable to execute JTAG queue");
+		return ERROR_FAIL;
+	}
+
+	for (size_t i = 0; i < batch->used_scans; ++i)
+		dump_field(batch->fields + i);
+
+	return ERROR_OK;
+}
+
+void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data)
+{
+	assert(batch->used_scans < batch->allocated_scans);
+	struct scan_field *field = batch->fields + batch->used_scans;
+	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
+	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	riscv_fill_dmi_write_u64(batch->target, (char *)field->out_value, address, data);
+	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
+	batch->last_scan = RISCV_SCAN_TYPE_WRITE;
+	batch->used_scans++;
+}
+
+size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address)
+{
+	assert(batch->used_scans < batch->allocated_scans);
+	struct scan_field *field = batch->fields + batch->used_scans;
+	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
+	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	riscv_fill_dmi_read_u64(batch->target, (char *)field->out_value, address);
+	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
+	batch->last_scan = RISCV_SCAN_TYPE_READ;
+	batch->used_scans++;
+
+	/* FIXME We get the read response back on the next scan.  For now I'm
+	 * just sticking a NOP in there, but this should be coelesced away. */
+	riscv_batch_add_nop(batch);
+
+	batch->read_keys[batch->read_keys_used] = batch->used_scans - 1;
+	LOG_DEBUG("read key %u for batch 0x%p is %u (0x%p)",
+			(unsigned) batch->read_keys_used, batch, (unsigned) (batch->used_scans - 1),
+			batch->data_in + sizeof(uint64_t) * (batch->used_scans + 1));
+	return batch->read_keys_used++;
+}
+
+uint64_t riscv_batch_get_dmi_read(struct riscv_batch *batch, size_t key)
+{
+	assert(key < batch->read_keys_used);
+	size_t index = batch->read_keys[key];
+	assert(index <= batch->used_scans);
+	uint8_t *base = batch->data_in + 8 * index;
+	return base[0] |
+		((uint64_t) base[1]) << 8 |
+		((uint64_t) base[2]) << 16 |
+		((uint64_t) base[3]) << 24 |
+		((uint64_t) base[4]) << 32 |
+		((uint64_t) base[5]) << 40 |
+		((uint64_t) base[6]) << 48 |
+		((uint64_t) base[7]) << 56;
+}
+
+void riscv_batch_add_nop(struct riscv_batch *batch)
+{
+	assert(batch->used_scans < batch->allocated_scans);
+	struct scan_field *field = batch->fields + batch->used_scans;
+	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
+	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	riscv_fill_dmi_nop_u64(batch->target, (char *)field->out_value);
+	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
+	batch->last_scan = RISCV_SCAN_TYPE_NOP;
+	batch->used_scans++;
+	LOG_DEBUG("  added NOP with in_value=0x%p", field->in_value);
+}
+
+void dump_field(const struct scan_field *field)
+{
+	static const char * const op_string[] = {"-", "r", "w", "?"};
+	static const char * const status_string[] = {"+", "?", "F", "b"};
+
+	if (debug_level < LOG_LVL_DEBUG)
+		return;
+
+	assert(field->out_value != NULL);
+	uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
+	unsigned int out_op = get_field(out, DTM_DMI_OP);
+	unsigned int out_data = get_field(out, DTM_DMI_DATA);
+	unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
+
+	if (field->in_value) {
+		uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
+		unsigned int in_op = get_field(in, DTM_DMI_OP);
+		unsigned int in_data = get_field(in, DTM_DMI_DATA);
+		unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
+
+		log_printf_lf(LOG_LVL_DEBUG,
+				__FILE__, __LINE__, __PRETTY_FUNCTION__,
+				"%db %s %08x @%02x -> %s %08x @%02x",
+				field->num_bits,
+				op_string[out_op], out_data, out_address,
+				status_string[in_op], in_data, in_address);
+	} else {
+		log_printf_lf(LOG_LVL_DEBUG,
+				__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
+				field->num_bits, op_string[out_op], out_data, out_address);
+	}
+}