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[BACKEND] Lowering i1 ptr to the PtrDialect on aipu #16

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[BACKEND] Lowering i1 ptr to the PtrDialect on aipu #16

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1 change: 1 addition & 0 deletions third_party/aipu/backend/compiler.py
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Expand Up @@ -100,6 +100,7 @@ def make_linalg(mod, metadata, opt):
pm.enable_debug()
# add pass here
aipu.passes.convert.add_triton_to_linalg_pipeline(pm)
aipu.passes.convert.add_triton_to_ptr(pm)
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@Lucien0 Lucien0 Jun 16, 2025

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Seems already in TritonToLinalgExperimentalPass, why here need do it again?

pm.run(mod)
return mod

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1 change: 1 addition & 0 deletions third_party/aipu/triton_aipu.cc
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Expand Up @@ -44,6 +44,7 @@ void init_triton_aipu_passes_convert(py::module &&m) {
ADD_PASS_WRAPPER_0("add_linalg_to_affine_loops",
createConvertLinalgToAffineLoopsPass);
ADD_PASS_WRAPPER_0("add_lower_affine", createLowerAffinePass);
ADD_PASS_WRAPPER_0("add_triton_to_ptr", triton::createTritonToPtrPass);

m.def("add_affine_vectorize", [](mlir::PassManager &pm, int64_t vecsize) {
affine::AffineVectorizeOptions vectorize_options;
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