Code Generation

Code generation takes the intermediate representation created in the previous step and converts it to the targeted assembly language. This compiler currently only has one assembly target: RISC-V 32bit.

For the most part code generation is as simple as converting basic blocks into labeled code and correctly turning the IR instructions into RISC-V instructions. The major challenge for this step is register allocation.

Register Allocation

The biggest difference between the IR language and an actual machine, is the IR's use of unlimited temporary registers. To convert this to executable assembly, requires we assign physical registers to each temporary variable and then free them for future use once a temporary is freed. As this was close to the end of the project, the part has been left mostly unfinished. A temporary solution has been implemented for testing purposes which involves never freeing temporary registers within a function, but this greatly restricts the size of functions as the compiler quickly runs out of assignable registers. A better solution to this would be to perform a liveness analysis on the IR to determine where the last usage of a temporary occurs and then linear scan register allocation to reduce the number of dead registers.