R5900 multimedia instructions (MMI)

The R5900 has a set of multimedia instructions (MMI) operating on the 128-bit general purpose registers (GPR). Each register is partitioned into parallel integer fields of 16×8 bits, 8×16 bits, 4×32 bits, or 2×64 bits, or floating-point fields of 4×32 bits, depending on the instruction.

The R5900 MMI architecture is similar to the MIPS SIMD architecture (MSA). Notable differences:

• R5900 MMI registers alias general purpose registers (GPRs), as opposed to floating-point registers as is the case for MSA.
• FIXME: R5900 MMIs are always enabled.
• FIXME: IEEE 754 compliancy, etc.

The base o32 and n32 MIPS ABIs are extended to allow use of R5900 MMIs. The ABI extension is compatible with the base ABIs in the sense that o32 and n32 machine code link and run unchanged on systems supporting R5900 MMIs, meaning there are no incompatibilities between the base o32 and n32 ABIs, and the extended R5900 MMI ABI. In particular, the extension doesn’t change the base ABI data types layout, alignment, nor calling convention (callee-saved, call-clobbered (temporary) or callee-saved status of the aliased GPRs). However, vector data types are considered part of the extended R5900 MMI ABI.

As a consequence, compiling for R5900 MMIs doesn’t change base ABIs vector calling conventions. Vector data types passed or returned by value don’t use the MMI vector registers. Rather, passing and returning vectors by value follow the calling conventions of the base ABI.

The base ABIs may seem to handle vectors inefficiently. However, optimisation features such as interprocedural optimisation should recover such losses.