Interface class shall not be nested within another interface class. (IEEE 1800-2023 8.26)

[s3rg1o7]

I get the following error when trying to run the example from examples/call/cocotb/call_sv_bfm

hdl_if/share/dpi/pyhdl_if_icall_api.svh:21:11: Interface class shall not be nested within another interface class. (IEEE 1800-2023 8.26)

My setup:

I am trying to run from within a conda environment, to mimic the setup I have in my project.

$ verilator --version
Verilator 5.038 2025-07-08 rev v5.038

$ pip list | grep pyhdl
pyhdl                         0.3.0

I've installed all the dependencies from the and in order to reach a point where I can run the make command I needed to do the following 3 steps:

1. install packages:

    pip install cython
    pip install setuptools_scm

2. set BUILD_NUM=1 by hand in src/hdl_if/build_num.py
3. ran

   ivpm update -a 
   python setup.py build_ext --inplace

4. modify examples/call/cocotb/call_sv_bfm/Makefile to add custom libraries:

   export PYTHONPATH := ../../../../src/:../../../../packages/:../../../../packages/pytypeworks/src/:$(PYTHONPATH)    
   

5. added missing signals err and sel to the init_bfm instantiation:

       ...
       
       wire[31:0] dat_r, dat_w;
       wire[31:0] adr;
       wire stb, cyc, we;
       wire err, sel;
       reg  ack_r;
       wire ack = (ack_r && cyc && stb);
       
       ...
   
       WishboneInitiatorBFM    init_bfm(
           .clock(clk),
           .reset(reset),
           .err(err),
           .sel(sel),
           .adr(adr),
           .dat_r(dat_r),
           .dat_w(dat_w),
           .stb(stb),
           .cyc(cyc),
           .ack(ack),
           .we(we)
       );
   
   endmodule

[mballance]

Hi @s3rg1o7, thanks for raising this issue.
This code worked as of Verilator 5.029 (and likely later), but I confirm that I see the same thing with Verilator 5.040. Because this code works with commerical SystemVerilog simulators, I'm inclined to view this as a bug in Verilator. If you're able to move back to an earlier version of Verilator, this may be a good workaround for now. I will also do some investigation on my side to narrow down the Verilator issue.

[mballance]

Quick update on this. Verilator 5.032 is the last version that works properly with this code 5.034..5.040 all report the nested interface-class error. Funny thing is, there is an interface class, but it is declared in package scope (not within another class).

[mballance]

Update: I've filed verilator/verilator#6549 on Verilator to track this issue.

[mballance]

I've released pyhdl-if v0.0.5 that contains a workaround for the Verilator issue. Specifically, explicitly importing pyhdl_if in the generated code and removing package-rooted references in a couple of places. The changes are compatible with other simulators as well.
Please try v0.0.5 and let me know if you face further issues.