zicond-refine

Author: lxq015

src/cmd/compile/internal/ssa/_gen/RISCV64.rules

@@ -860,8 +860,8 @@
 (Min64u x y) && buildcfg.GORISCV64 >= 22 => (MINU x y)
 (Max64u x y) && buildcfg.GORISCV64 >= 22 => (MAXU x y)
 
-// Zicond Extension for Integer Conditional Operations
-(CondSelect <t> x y cond) && buildcfg.GORISCV64 >= 23 =>
+// Conditional selection (note that these will only be emitted for rva23u64 and above)
+(CondSelect <t> x y cond) =>
 	(OR (CZEROEQZ <t> x (MOVBUreg <typ.UInt64> cond)) (CZERONEZ <t> y (MOVBUreg <typ.UInt64> cond)))
 (CZERO(EQ|NE)Z x (SNEZ y)) => (CZERO(EQ|NE)Z x y)
 (CZERO(EQ|NE)Z x (SEQZ y)) => (CZERO(NE|EQ)Z x y)
@@ -870,11 +870,11 @@
 (CZERO(EQ|NE)Z (MOVDconst [0]) _) => (MOVDconst [0])
 
 // Optimize conditional arithmetic operations
-(OR (CZERONEZ <t> ((ADD|SUB|OR|XOR|SUBW) x y) cond) (CZEROEQZ <t> x cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZERONEZ <t> y cond))
+(OR (CZEROEQZ <t> x cond) (CZERONEZ <t> ((ADD|SUB|OR|XOR|SUBW) x y) cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZERONEZ <t> y cond))
 (OR (CZEROEQZ <t> ((ADD|SUB|OR|XOR|SUBW) x y) cond) (CZERONEZ <t> x cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZEROEQZ <t> y cond))
-(OR (CZERONEZ x:(AND z _) cond) y:(CZEROEQZ z cond)) => (OR x y)
+(OR x:(CZEROEQZ z cond) (CZERONEZ y:(AND z _) cond)) => (OR y x)
 (OR (CZEROEQZ x:(AND z _) cond) y:(CZERONEZ z cond)) => (OR x y)
-(OR (CZERONEZ x:(ANDI <t> [c] z) cond) y:(CZEROEQZ z cond)) => (OR x y)
+(OR x:(CZEROEQZ z cond) (CZERONEZ y:(ANDI <t> [c] z) cond)) => (OR y x)
 (OR (CZEROEQZ x:(ANDI <t> [c] z) cond) y:(CZERONEZ z cond)) => (OR x y)
-(OR (CZERONEZ <t> ((ADDI|ORI|XORI) [c] x) cond) (CZEROEQZ <t> x cond)) => ((ADD|OR|XOR) x (CZERONEZ <t> (MOVDconst [c]) cond))
+(OR (CZEROEQZ <t> x cond) (CZERONEZ <t> ((ADDI|ORI|XORI) [c] x) cond)) => ((ADD|OR|XOR) x (CZERONEZ <t> (MOVDconst [c]) cond))
 (OR (CZEROEQZ <t> ((ADDI|ORI|XORI) [c] x) cond) (CZERONEZ <t> x cond)) => ((ADD|OR|XOR) x (CZEROEQZ <t> (MOVDconst [c]) cond))

src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

@@ -525,8 +525,8 @@ func init() {
 		{name: "FCLASSD", argLength: 1, reg: fpgp, asm: "FCLASSD", typ: "Int64"}, // classify float64
 
 		// RISC-V Integer Conditional (Zicond) operations extension
-		{name: "CZEROEQZ", argLength: 2, reg: gp21, asm: "CZEROEQZ"},
-		{name: "CZERONEZ", argLength: 2, reg: gp21, asm: "CZERONEZ"},
+		{name: "CZEROEQZ", argLength: 2, reg: gp21, asm: "CZEROEQZ"}, // arg1 == 0 result is 0, else arg0
+		{name: "CZERONEZ", argLength: 2, reg: gp21, asm: "CZERONEZ"}, // arg1 != 0 result is 0, else arg0
 	}
 
 	RISCV64blocks := []blockData{