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TE-N-ShengjiuWanggregkh
TE-N-ShengjiuWang
authored and
gregkh
committed
ASoC: fsl_easrc: Change the type for iec958 channel status controls
[ Upstream commit 47f28a5 ] Use the type SNDRV_CTL_ELEM_TYPE_IEC958 for iec958 channel status controls, the original type will cause mixer-test to iterate all 32bit values, which costs a lot of time. And using IEC958 type can reduce the control numbers. Also enable pm runtime before updating registers to make the regmap cache data align with the value in hardware. Fixes: 955ac62 ("ASoC: fsl_easrc: Add EASRC ASoC CPU DAI drivers") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/20260401094226.2900532-12-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
1 parent 8a808a1 commit 010b108

1 file changed

Lines changed: 84 additions & 34 deletions

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‎sound/soc/fsl/fsl_easrc.c‎

Lines changed: 84 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -78,17 +78,47 @@ static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
7878
return 0;
7979
}
8080

81+
static int fsl_easrc_iec958_info(struct snd_kcontrol *kcontrol,
82+
struct snd_ctl_elem_info *uinfo)
83+
{
84+
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
85+
uinfo->count = 1;
86+
return 0;
87+
}
88+
8189
static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
8290
struct snd_ctl_elem_value *ucontrol)
8391
{
8492
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
8593
struct soc_mreg_control *mc =
8694
(struct soc_mreg_control *)kcontrol->private_value;
87-
unsigned int regval;
95+
struct fsl_asrc *easrc = snd_soc_component_get_drvdata(component);
96+
unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;
97+
int ret;
98+
99+
ret = regmap_read(easrc->regmap, REG_EASRC_CS0(mc->regbase), &regval[0]);
100+
if (ret)
101+
return ret;
102+
103+
ret = regmap_read(easrc->regmap, REG_EASRC_CS1(mc->regbase), &regval[1]);
104+
if (ret)
105+
return ret;
106+
107+
ret = regmap_read(easrc->regmap, REG_EASRC_CS2(mc->regbase), &regval[2]);
108+
if (ret)
109+
return ret;
88110

89-
regval = snd_soc_component_read(component, mc->regbase);
111+
ret = regmap_read(easrc->regmap, REG_EASRC_CS3(mc->regbase), &regval[3]);
112+
if (ret)
113+
return ret;
114+
115+
ret = regmap_read(easrc->regmap, REG_EASRC_CS4(mc->regbase), &regval[4]);
116+
if (ret)
117+
return ret;
90118

91-
ucontrol->value.integer.value[0] = regval;
119+
ret = regmap_read(easrc->regmap, REG_EASRC_CS5(mc->regbase), &regval[5]);
120+
if (ret)
121+
return ret;
92122

93123
return 0;
94124
}
@@ -100,22 +130,62 @@ static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
100130
struct soc_mreg_control *mc =
101131
(struct soc_mreg_control *)kcontrol->private_value;
102132
struct fsl_asrc *easrc = snd_soc_component_get_drvdata(component);
103-
unsigned int regval = ucontrol->value.integer.value[0];
104-
bool changed;
133+
unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;
134+
bool changed, changed_all = false;
105135
int ret;
106136

107-
ret = regmap_update_bits_check(easrc->regmap, mc->regbase,
108-
GENMASK(31, 0), regval, &changed);
109-
if (ret != 0)
137+
ret = pm_runtime_resume_and_get(component->dev);
138+
if (ret)
110139
return ret;
111140

112-
return changed;
141+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS0(mc->regbase),
142+
GENMASK(31, 0), regval[0], &changed);
143+
if (ret != 0)
144+
goto err;
145+
changed_all |= changed;
146+
147+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS1(mc->regbase),
148+
GENMASK(31, 0), regval[1], &changed);
149+
if (ret != 0)
150+
goto err;
151+
changed_all |= changed;
152+
153+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS2(mc->regbase),
154+
GENMASK(31, 0), regval[2], &changed);
155+
if (ret != 0)
156+
goto err;
157+
changed_all |= changed;
158+
159+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS3(mc->regbase),
160+
GENMASK(31, 0), regval[3], &changed);
161+
if (ret != 0)
162+
goto err;
163+
changed_all |= changed;
164+
165+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS4(mc->regbase),
166+
GENMASK(31, 0), regval[4], &changed);
167+
if (ret != 0)
168+
goto err;
169+
changed_all |= changed;
170+
171+
ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS5(mc->regbase),
172+
GENMASK(31, 0), regval[5], &changed);
173+
if (ret != 0)
174+
goto err;
175+
changed_all |= changed;
176+
err:
177+
pm_runtime_put_autosuspend(component->dev);
178+
179+
if (ret != 0)
180+
return ret;
181+
else
182+
return changed_all;
113183
}
114184

115185
#define SOC_SINGLE_REG_RW(xname, xreg) \
116186
{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
117187
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
118-
.info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
188+
.info = fsl_easrc_iec958_info, .get = fsl_easrc_get_reg, \
119189
.put = fsl_easrc_set_reg, \
120190
.private_value = (unsigned long)&(struct soc_mreg_control) \
121191
{ .regbase = xreg, .regcount = 1, .nbits = 32, \
@@ -146,30 +216,10 @@ static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
146216
SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
147217
SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
148218

149-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
150-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
151-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
152-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
153-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
154-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
155-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
156-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
157-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
158-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
159-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
160-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
161-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
162-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
163-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
164-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
165-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
166-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
167-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
168-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
169-
SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
170-
SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
171-
SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
172-
SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
219+
SOC_SINGLE_REG_RW("Context 0 IEC958 CS", 0),
220+
SOC_SINGLE_REG_RW("Context 1 IEC958 CS", 1),
221+
SOC_SINGLE_REG_RW("Context 2 IEC958 CS", 2),
222+
SOC_SINGLE_REG_RW("Context 3 IEC958 CS", 3),
173223
};
174224

175225
/*

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