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Victor Shihgregkh
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mmc: sdhci-pci-gli: Add a new function to simplify the code
commit dec8b38 upstream. In preparation to fix replay timer timeout, add sdhci_gli_mask_replay_timer_timeout() function to simplify some of the code, allowing it to be re-used. Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> Fixes: 1ae1d2d ("mmc: sdhci-pci-gli: Add Genesys Logic GL9763E support") Cc: stable@vger.kernel.org Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20250731065752.450231-2-victorshihgli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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drivers/mmc/host/sdhci-pci-gli.c

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,20 @@
287287
#define GLI_MAX_TUNING_LOOP 40
288288

289289
/* Genesys Logic chipset */
290+
static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev)
291+
{
292+
int aer;
293+
u32 value;
294+
295+
/* mask the replay timer timeout of AER */
296+
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
297+
if (aer) {
298+
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
299+
value |= PCI_ERR_COR_REP_TIMER;
300+
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
301+
}
302+
}
303+
290304
static inline void gl9750_wt_on(struct sdhci_host *host)
291305
{
292306
u32 wt_value;
@@ -607,7 +621,6 @@ static void gl9750_hw_setting(struct sdhci_host *host)
607621
{
608622
struct sdhci_pci_slot *slot = sdhci_priv(host);
609623
struct pci_dev *pdev;
610-
int aer;
611624
u32 value;
612625

613626
pdev = slot->chip->pdev;
@@ -626,12 +639,7 @@ static void gl9750_hw_setting(struct sdhci_host *host)
626639
pci_set_power_state(pdev, PCI_D0);
627640

628641
/* mask the replay timer timeout of AER */
629-
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
630-
if (aer) {
631-
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
632-
value |= PCI_ERR_COR_REP_TIMER;
633-
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
634-
}
642+
sdhci_gli_mask_replay_timer_timeout(pdev);
635643

636644
gl9750_wt_off(host);
637645
}
@@ -806,7 +814,6 @@ static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
806814
static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
807815
{
808816
struct pci_dev *pdev = slot->chip->pdev;
809-
int aer;
810817
u32 value;
811818

812819
gl9755_wt_on(pdev);
@@ -841,12 +848,7 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
841848
pci_set_power_state(pdev, PCI_D0);
842849

843850
/* mask the replay timer timeout of AER */
844-
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
845-
if (aer) {
846-
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
847-
value |= PCI_ERR_COR_REP_TIMER;
848-
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
849-
}
851+
sdhci_gli_mask_replay_timer_timeout(pdev);
850852

851853
gl9755_wt_off(pdev);
852854
}

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