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Commit 824253d

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Fuad Tabbagregkh
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KVM: arm64: Fix FEAT_SPE_FnE to use PMSIDR_EL1.FnE, not PMSVer
commit 08d7153 upstream. FEAT_SPE_FnE is architecturally detected via PMSIDR_EL1.FnE [6], not ID_AA64DFR0_EL1.PMSVer. The FEAT_X macro form (register, field, value) cannot encode a PMSIDR_EL1-based feature, so FEAT_SPE_FnE was defined identically to FEAT_SPEv1p2 (ID_AA64DFR0_EL1, PMSVer, V1P2), producing a duplicate that used PMSVer >= V1P2 as a proxy. Replace the macro with feat_spe_fne(), following the same pattern as the sibling feat_spe_fds(): guard on FEAT_SPEv1p2 and read PMSIDR_EL1.FnE [6] directly. Wire the two NEEDS_FEAT consumers to use the new function. Remove the now-unused FEAT_SPE_FnE macro. Fixes: 63d423a ("KVM: arm64: Switch to table-driven FGU configuration") Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260424084908.370776-4-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lines changed: 12 additions & 3 deletions

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arch/arm64/kvm/config.c

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,6 @@ struct reg_feat_map_desc {
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}
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#define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP
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#define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2
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#define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP
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#define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP
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#define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP
@@ -301,6 +300,16 @@ static bool feat_spe_fds(struct kvm *kvm)
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(read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS));
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}
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static bool feat_spe_fne(struct kvm *kvm)
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{
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/*
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* Revisit this if KVM ever supports SPE -- this really should
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* look at the guest's view of PMSIDR_EL1.
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*/
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return (kvm_has_feat(kvm, FEAT_SPEv1p2) &&
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(read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FnE));
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}
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static bool feat_trbe_mpam(struct kvm *kvm)
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{
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/*
@@ -536,7 +545,7 @@ static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = {
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HDFGRTR_EL2_PMBPTR_EL1 |
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HDFGRTR_EL2_PMBLIMITR_EL1,
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FEAT_SPE),
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NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE),
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NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
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NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA |
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HDFGRTR_EL2_nBRBCTL |
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HDFGRTR_EL2_nBRBIDR,
@@ -604,7 +613,7 @@ static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = {
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HDFGWTR_EL2_PMBPTR_EL1 |
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HDFGWTR_EL2_PMBLIMITR_EL1,
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FEAT_SPE),
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NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE),
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NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
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NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA |
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HDFGWTR_EL2_nBRBCTL,
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FEAT_BRBE),

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