Skip to content

Commit 8516332

Browse files
tq-schifferngregkh
authored andcommitted
arm64: dts: freescale: imx8mp-tqma8mpql-mba8mp-ras314: fix UART1 RTS/CTS muxing
[ Upstream commit b8d785a ] UART1 operates in DCE mode, but the RTS/CTS pins were incorrectly configured using the DTE pinmux setting. Correct the pinmux to match DCE mode. Switching the RTS and CTS signals is fine for this board, as UART1 is routed to a pin header. Existing functionality is unaffected, as RTS/CTS could never have worked with the incorrect pinmux. Fixes: ddabb3c ("arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314") Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
1 parent 4675ae6 commit 8516332

1 file changed

Lines changed: 2 additions & 2 deletions

File tree

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -833,8 +833,8 @@
833833
pinctrl_uart1: uart1grp {
834834
fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
835835
<MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
836-
<MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
837-
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
836+
<MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x14>,
837+
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x14>;
838838
};
839839

840840
pinctrl_uart1_gpio: uart1gpiogrp {

0 commit comments

Comments
 (0)