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Timur Kristófgregkh
Timur Kristóf
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gregkh
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drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming.
commit 1c8dc3e upstream. Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 35222b5) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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‎drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -245,6 +245,11 @@ int dce_set_clock(
245245
pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
246246
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
247247

248+
/* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */
249+
if (clk_mgr_base->ctx->dce_version == DCE_VERSION_6_0 ||
250+
clk_mgr_base->ctx->dce_version == DCE_VERSION_6_4)
251+
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0;
252+
248253
if (clk_mgr_dce->dfs_bypass_active)
249254
pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
250255

‎drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c‎

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -373,7 +373,7 @@ static const struct resource_caps res_cap = {
373373
.num_timing_generator = 6,
374374
.num_audio = 6,
375375
.num_stream_encoder = 6,
376-
.num_pll = 2,
376+
.num_pll = 3,
377377
.num_ddc = 6,
378378
};
379379

@@ -389,7 +389,7 @@ static const struct resource_caps res_cap_64 = {
389389
.num_timing_generator = 2,
390390
.num_audio = 2,
391391
.num_stream_encoder = 2,
392-
.num_pll = 2,
392+
.num_pll = 3,
393393
.num_ddc = 2,
394394
};
395395

@@ -973,21 +973,24 @@ static bool dce60_construct(
973973

974974
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
975975
pool->base.dp_clock_source =
976-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
976+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
977977

978+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
978979
pool->base.clock_sources[0] =
979-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
980+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
980981
pool->base.clock_sources[1] =
981-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
982+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
982983
pool->base.clk_src_count = 2;
983984

984985
} else {
985986
pool->base.dp_clock_source =
986-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
987+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
987988

988989
pool->base.clock_sources[0] =
989-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
990-
pool->base.clk_src_count = 1;
990+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
991+
pool->base.clock_sources[1] =
992+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
993+
pool->base.clk_src_count = 2;
991994
}
992995

993996
if (pool->base.dp_clock_source == NULL) {
@@ -1365,21 +1368,24 @@ static bool dce64_construct(
13651368

13661369
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
13671370
pool->base.dp_clock_source =
1368-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1371+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
13691372

1373+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
13701374
pool->base.clock_sources[0] =
1371-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1375+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
13721376
pool->base.clock_sources[1] =
1373-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1377+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
13741378
pool->base.clk_src_count = 2;
13751379

13761380
} else {
13771381
pool->base.dp_clock_source =
1378-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1382+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
13791383

13801384
pool->base.clock_sources[0] =
1381-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1382-
pool->base.clk_src_count = 1;
1385+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1386+
pool->base.clock_sources[1] =
1387+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1388+
pool->base.clk_src_count = 2;
13831389
}
13841390

13851391
if (pool->base.dp_clock_source == NULL) {

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