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shinas-marvellSasha Levin
shinas-marvell
authored and
Sasha Levin
committed
octeon_ep: restructured interrupt handlers
[ Upstream commit 0b8ef82 ] Separated queue specific interrupts to register to individual msix-vectors instead of using a single generic interrupt handler on a single msix-vector. Signed-off-by: Shinas Rasheed <srasheed@marvell.com> Link: https://lore.kernel.org/r/20230918065621.2165449-1-srasheed@marvell.com Signed-off-by: Paolo Abeni <pabeni@redhat.com> Stable-dep-of: 73e6ffa ("octeon_ep: disable per ring interrupts") Signed-off-by: Sasha Levin <sashal@kernel.org>
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3 files changed

+323
-45
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3 files changed

+323
-45
lines changed

‎drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c‎

Lines changed: 122 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -369,34 +369,40 @@ static void octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no)
369369
mbox->mbox_read_reg = oct->mmio[0].hw_addr + CN93_SDP_R_MBOX_VF_PF_DATA(q_no);
370370
}
371371

372-
/* Process non-ioq interrupts required to keep pf interface running.
373-
* OEI_RINT is needed for control mailbox
374-
*/
375-
static bool octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct)
376-
{
377-
bool handled = false;
378-
u64 reg0;
379-
380-
/* Check for OEI INTR */
381-
reg0 = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT);
382-
if (reg0) {
383-
dev_info(&oct->pdev->dev,
384-
"Received OEI_RINT intr: 0x%llx\n",
385-
reg0);
386-
octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg0);
387-
if (reg0 & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)
372+
/* Poll OEI events like heartbeat */
373+
static void octep_poll_oei_cn93_pf(struct octep_device *oct)
374+
{
375+
u64 reg;
376+
377+
reg = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT);
378+
if (reg) {
379+
octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg);
380+
if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)
388381
queue_work(octep_wq, &oct->ctrl_mbox_task);
389-
else if (reg0 & CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT)
382+
else if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT)
390383
atomic_set(&oct->hb_miss_cnt, 0);
391-
392-
handled = true;
393384
}
385+
}
386+
387+
/* OEI interrupt handler */
388+
static irqreturn_t octep_oei_intr_handler_cn93_pf(void *dev)
389+
{
390+
struct octep_device *oct = (struct octep_device *)dev;
394391

395-
return handled;
392+
octep_poll_oei_cn93_pf(oct);
393+
return IRQ_HANDLED;
394+
}
395+
396+
/* Process non-ioq interrupts required to keep pf interface running.
397+
* OEI_RINT is needed for control mailbox
398+
*/
399+
static void octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct)
400+
{
401+
octep_poll_oei_cn93_pf(oct);
396402
}
397403

398-
/* Interrupts handler for all non-queue generic interrupts. */
399-
static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev)
404+
/* Interrupt handler for input ring error interrupts. */
405+
static irqreturn_t octep_ire_intr_handler_cn93_pf(void *dev)
400406
{
401407
struct octep_device *oct = (struct octep_device *)dev;
402408
struct pci_dev *pdev = oct->pdev;
@@ -421,8 +427,17 @@ static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev)
421427
reg_val);
422428
}
423429
}
424-
goto irq_handled;
425430
}
431+
return IRQ_HANDLED;
432+
}
433+
434+
/* Interrupt handler for output ring error interrupts. */
435+
static irqreturn_t octep_ore_intr_handler_cn93_pf(void *dev)
436+
{
437+
struct octep_device *oct = (struct octep_device *)dev;
438+
struct pci_dev *pdev = oct->pdev;
439+
u64 reg_val = 0;
440+
int i = 0;
426441

427442
/* Check for ORERR INTR */
428443
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_ORERR_RINT);
@@ -440,68 +455,116 @@ static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev)
440455
reg_val);
441456
}
442457
}
443-
444-
goto irq_handled;
445458
}
459+
return IRQ_HANDLED;
460+
}
461+
462+
/* Interrupt handler for vf input ring error interrupts. */
463+
static irqreturn_t octep_vfire_intr_handler_cn93_pf(void *dev)
464+
{
465+
struct octep_device *oct = (struct octep_device *)dev;
466+
struct pci_dev *pdev = oct->pdev;
467+
u64 reg_val = 0;
446468

447469
/* Check for VFIRE INTR */
448470
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0));
449471
if (reg_val) {
450472
dev_info(&pdev->dev,
451473
"Received VFIRE_RINT intr: 0x%llx\n", reg_val);
452474
octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0), reg_val);
453-
goto irq_handled;
454475
}
476+
return IRQ_HANDLED;
477+
}
478+
479+
/* Interrupt handler for vf output ring error interrupts. */
480+
static irqreturn_t octep_vfore_intr_handler_cn93_pf(void *dev)
481+
{
482+
struct octep_device *oct = (struct octep_device *)dev;
483+
struct pci_dev *pdev = oct->pdev;
484+
u64 reg_val = 0;
455485

456486
/* Check for VFORE INTR */
457487
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0));
458488
if (reg_val) {
459489
dev_info(&pdev->dev,
460490
"Received VFORE_RINT intr: 0x%llx\n", reg_val);
461491
octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0), reg_val);
462-
goto irq_handled;
463492
}
493+
return IRQ_HANDLED;
494+
}
464495

465-
/* Check for MBOX INTR and OEI INTR */
466-
if (octep_poll_non_ioq_interrupts_cn93_pf(oct))
467-
goto irq_handled;
496+
/* Interrupt handler for dpi dma related interrupts. */
497+
static irqreturn_t octep_dma_intr_handler_cn93_pf(void *dev)
498+
{
499+
struct octep_device *oct = (struct octep_device *)dev;
500+
u64 reg_val = 0;
468501

469502
/* Check for DMA INTR */
470503
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT);
471504
if (reg_val) {
472505
octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT, reg_val);
473-
goto irq_handled;
474506
}
507+
return IRQ_HANDLED;
508+
}
509+
510+
/* Interrupt handler for dpi dma transaction error interrupts for VFs */
511+
static irqreturn_t octep_dma_vf_intr_handler_cn93_pf(void *dev)
512+
{
513+
struct octep_device *oct = (struct octep_device *)dev;
514+
struct pci_dev *pdev = oct->pdev;
515+
u64 reg_val = 0;
475516

476517
/* Check for DMA VF INTR */
477518
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0));
478519
if (reg_val) {
479520
dev_info(&pdev->dev,
480521
"Received DMA_VF_RINT intr: 0x%llx\n", reg_val);
481522
octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0), reg_val);
482-
goto irq_handled;
483523
}
524+
return IRQ_HANDLED;
525+
}
526+
527+
/* Interrupt handler for pp transaction error interrupts for VFs */
528+
static irqreturn_t octep_pp_vf_intr_handler_cn93_pf(void *dev)
529+
{
530+
struct octep_device *oct = (struct octep_device *)dev;
531+
struct pci_dev *pdev = oct->pdev;
532+
u64 reg_val = 0;
484533

485534
/* Check for PPVF INTR */
486535
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0));
487536
if (reg_val) {
488537
dev_info(&pdev->dev,
489538
"Received PP_VF_RINT intr: 0x%llx\n", reg_val);
490539
octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0), reg_val);
491-
goto irq_handled;
492540
}
541+
return IRQ_HANDLED;
542+
}
543+
544+
/* Interrupt handler for mac related interrupts. */
545+
static irqreturn_t octep_misc_intr_handler_cn93_pf(void *dev)
546+
{
547+
struct octep_device *oct = (struct octep_device *)dev;
548+
struct pci_dev *pdev = oct->pdev;
549+
u64 reg_val = 0;
493550

494551
/* Check for MISC INTR */
495552
reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MISC_RINT);
496553
if (reg_val) {
497554
dev_info(&pdev->dev,
498555
"Received MISC_RINT intr: 0x%llx\n", reg_val);
499556
octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT, reg_val);
500-
goto irq_handled;
501557
}
558+
return IRQ_HANDLED;
559+
}
560+
561+
/* Interrupts handler for all reserved interrupts. */
562+
static irqreturn_t octep_rsvd_intr_handler_cn93_pf(void *dev)
563+
{
564+
struct octep_device *oct = (struct octep_device *)dev;
565+
struct pci_dev *pdev = oct->pdev;
502566

503567
dev_info(&pdev->dev, "Reserved interrupts raised; Ignore\n");
504-
irq_handled:
505568
return IRQ_HANDLED;
506569
}
507570

@@ -565,8 +628,15 @@ static void octep_enable_interrupts_cn93_pf(struct octep_device *oct)
565628
octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1S, intr_mask);
566629
octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1S, intr_mask);
567630
octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1S, -1ULL);
631+
632+
octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(0), -1ULL);
633+
octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1S(0), -1ULL);
634+
568635
octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask);
569636
octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask);
637+
638+
octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL);
639+
octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL);
570640
}
571641

572642
/* Disable all interrupts */
@@ -584,8 +654,15 @@ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)
584654
octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);
585655
octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);
586656
octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1C, -1ULL);
657+
658+
octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(0), -1ULL);
659+
octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1C(0), -1ULL);
660+
587661
octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask);
588662
octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask);
663+
664+
octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL);
665+
octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL);
589666
}
590667

591668
/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
@@ -718,7 +795,16 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)
718795
oct->hw_ops.setup_oq_regs = octep_setup_oq_regs_cn93_pf;
719796
oct->hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cn93_pf;
720797

721-
oct->hw_ops.non_ioq_intr_handler = octep_non_ioq_intr_handler_cn93_pf;
798+
oct->hw_ops.oei_intr_handler = octep_oei_intr_handler_cn93_pf;
799+
oct->hw_ops.ire_intr_handler = octep_ire_intr_handler_cn93_pf;
800+
oct->hw_ops.ore_intr_handler = octep_ore_intr_handler_cn93_pf;
801+
oct->hw_ops.vfire_intr_handler = octep_vfire_intr_handler_cn93_pf;
802+
oct->hw_ops.vfore_intr_handler = octep_vfore_intr_handler_cn93_pf;
803+
oct->hw_ops.dma_intr_handler = octep_dma_intr_handler_cn93_pf;
804+
oct->hw_ops.dma_vf_intr_handler = octep_dma_vf_intr_handler_cn93_pf;
805+
oct->hw_ops.pp_vf_intr_handler = octep_pp_vf_intr_handler_cn93_pf;
806+
oct->hw_ops.misc_intr_handler = octep_misc_intr_handler_cn93_pf;
807+
oct->hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cn93_pf;
722808
oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf;
723809
oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf;
724810
oct->hw_ops.reinit_regs = octep_reinit_regs_cn93_pf;

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