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srishanmSasha Levin
srishanm
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Sasha Levin
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drm/amdgpu: Use explicit VCN instance 0 in SR-IOV init
[ Upstream commit af26fa7 ] vcn_v2_0_start_sriov() declares a local variable "i" initialized to zero and uses it only as the instance index in SOC15_REG_OFFSET(UVD, i, ...). The value is never changed and all other fields are taken from adev->vcn.inst[0], so this path only ever programs VCN instance 0. This triggered a Smatch: warn: iterator 'i' not incremented Replace the dummy iterator with an explicit instance index of 0 in SOC15_REG_OFFSET() calls. Fixes: dd26858 ("drm/amdgpu: implement initialization part on VCN2.0 for SRIOV") Reported by: Dan Carpenter <dan.carpenter@linaro.org> Cc: darlington Opara <darlington.opara@amd.com> Cc: Jinage Zhao <jiange.zhao@amd.com> Cc: Monk Liu <Monk.Liu@amd.com> Cc: Emily Deng <Emily.Deng@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c‎

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1861,7 +1861,8 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
18611861
struct mmsch_v2_0_cmd_end end = { {0} };
18621862
struct mmsch_v2_0_init_header *header;
18631863
uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1864-
uint8_t i = 0;
1864+
1865+
/* This path only programs VCN instance 0. */
18651866

18661867
header = (struct mmsch_v2_0_init_header *)init_table;
18671868
direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
@@ -1880,93 +1881,93 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
18801881
size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
18811882

18821883
MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1883-
SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1884+
SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
18841885
0xFFFFFFFF, 0x00000004);
18851886

18861887
/* mc resume*/
18871888
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
18881889
MMSCH_V2_0_INSERT_DIRECT_WT(
1889-
SOC15_REG_OFFSET(UVD, i,
1890+
SOC15_REG_OFFSET(UVD, 0,
18901891
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
18911892
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
18921893
MMSCH_V2_0_INSERT_DIRECT_WT(
1893-
SOC15_REG_OFFSET(UVD, i,
1894+
SOC15_REG_OFFSET(UVD, 0,
18941895
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
18951896
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
18961897
offset = 0;
18971898
} else {
18981899
MMSCH_V2_0_INSERT_DIRECT_WT(
1899-
SOC15_REG_OFFSET(UVD, i,
1900+
SOC15_REG_OFFSET(UVD, 0,
19001901
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
19011902
lower_32_bits(adev->vcn.inst->gpu_addr));
19021903
MMSCH_V2_0_INSERT_DIRECT_WT(
1903-
SOC15_REG_OFFSET(UVD, i,
1904+
SOC15_REG_OFFSET(UVD, 0,
19041905
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
19051906
upper_32_bits(adev->vcn.inst->gpu_addr));
19061907
offset = size;
19071908
}
19081909

19091910
MMSCH_V2_0_INSERT_DIRECT_WT(
1910-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1911+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
19111912
0);
19121913
MMSCH_V2_0_INSERT_DIRECT_WT(
1913-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1914+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0),
19141915
size);
19151916

19161917
MMSCH_V2_0_INSERT_DIRECT_WT(
1917-
SOC15_REG_OFFSET(UVD, i,
1918+
SOC15_REG_OFFSET(UVD, 0,
19181919
mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
19191920
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
19201921
MMSCH_V2_0_INSERT_DIRECT_WT(
1921-
SOC15_REG_OFFSET(UVD, i,
1922+
SOC15_REG_OFFSET(UVD, 0,
19221923
mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
19231924
upper_32_bits(adev->vcn.inst->gpu_addr + offset));
19241925
MMSCH_V2_0_INSERT_DIRECT_WT(
1925-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1926+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1),
19261927
0);
19271928
MMSCH_V2_0_INSERT_DIRECT_WT(
1928-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1929+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1),
19291930
AMDGPU_VCN_STACK_SIZE);
19301931

19311932
MMSCH_V2_0_INSERT_DIRECT_WT(
1932-
SOC15_REG_OFFSET(UVD, i,
1933+
SOC15_REG_OFFSET(UVD, 0,
19331934
mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
19341935
lower_32_bits(adev->vcn.inst->gpu_addr + offset +
19351936
AMDGPU_VCN_STACK_SIZE));
19361937
MMSCH_V2_0_INSERT_DIRECT_WT(
1937-
SOC15_REG_OFFSET(UVD, i,
1938+
SOC15_REG_OFFSET(UVD, 0,
19381939
mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
19391940
upper_32_bits(adev->vcn.inst->gpu_addr + offset +
19401941
AMDGPU_VCN_STACK_SIZE));
19411942
MMSCH_V2_0_INSERT_DIRECT_WT(
1942-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1943+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2),
19431944
0);
19441945
MMSCH_V2_0_INSERT_DIRECT_WT(
1945-
SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1946+
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
19461947
AMDGPU_VCN_CONTEXT_SIZE);
19471948

19481949
for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
19491950
ring = &adev->vcn.inst->ring_enc[r];
19501951
ring->wptr = 0;
19511952
MMSCH_V2_0_INSERT_DIRECT_WT(
1952-
SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1953+
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO),
19531954
lower_32_bits(ring->gpu_addr));
19541955
MMSCH_V2_0_INSERT_DIRECT_WT(
1955-
SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1956+
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI),
19561957
upper_32_bits(ring->gpu_addr));
19571958
MMSCH_V2_0_INSERT_DIRECT_WT(
1958-
SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1959+
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE),
19591960
ring->ring_size / 4);
19601961
}
19611962

19621963
ring = &adev->vcn.inst->ring_dec;
19631964
ring->wptr = 0;
19641965
MMSCH_V2_0_INSERT_DIRECT_WT(
1965-
SOC15_REG_OFFSET(UVD, i,
1966+
SOC15_REG_OFFSET(UVD, 0,
19661967
mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
19671968
lower_32_bits(ring->gpu_addr));
19681969
MMSCH_V2_0_INSERT_DIRECT_WT(
1969-
SOC15_REG_OFFSET(UVD, i,
1970+
SOC15_REG_OFFSET(UVD, 0,
19701971
mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
19711972
upper_32_bits(ring->gpu_addr));
19721973
/* force RBC into idle state */
@@ -1977,7 +1978,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
19771978
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
19781979
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
19791980
MMSCH_V2_0_INSERT_DIRECT_WT(
1980-
SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1981+
SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
19811982

19821983
/* add end packet */
19831984
tmp = sizeof(struct mmsch_v2_0_cmd_end);

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