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Yang Yinglianggregkh
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spi: zynq-qspi: switch to use modern name
[ Upstream commit 178ebb0 ] Change legacy name master/slave to modern name host/target or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://msgid.link/r/20231128093031.3707034-24-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org> Stable-dep-of: c9c0127 ("spi: zynq-qspi: fix controller deregistration") Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent db96551 commit ae6ee9f

1 file changed

Lines changed: 14 additions & 14 deletions

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drivers/spi/spi-zynq-qspi.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,10 @@
5454
#define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
5555

5656
/*
57-
* QSPI Configuration Register - Baud rate and slave select
57+
* QSPI Configuration Register - Baud rate and target select
5858
*
5959
* These are the values used in the calculation of baud rate divisor and
60-
* setting the slave select.
60+
* setting the target select.
6161
*/
6262
#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
6363
#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
@@ -164,14 +164,14 @@ static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
164164
*
165165
* The default settings of the QSPI controller's configurable parameters on
166166
* reset are
167-
* - Master mode
167+
* - Host mode
168168
* - Baud rate divisor is set to 2
169169
* - Tx threshold set to 1l Rx threshold set to 32
170170
* - Flash memory interface mode enabled
171171
* - Size of the word to be transferred as 8 bit
172172
* This function performs the following actions
173173
* - Disable and clear all the interrupts
174-
* - Enable manual slave select
174+
* - Enable manual target select
175175
* - Enable manual start
176176
* - Deselect all the chip select lines
177177
* - Set the size of the word to be transferred as 32 bit
@@ -289,7 +289,7 @@ static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
289289
*/
290290
static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
291291
{
292-
struct spi_controller *ctlr = spi->master;
292+
struct spi_controller *ctlr = spi->controller;
293293
struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
294294
u32 config_reg;
295295

@@ -377,7 +377,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
377377
*/
378378
static int zynq_qspi_setup_op(struct spi_device *spi)
379379
{
380-
struct spi_controller *ctlr = spi->master;
380+
struct spi_controller *ctlr = spi->controller;
381381
struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
382382
int ret;
383383

@@ -534,7 +534,7 @@ static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
534534
static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
535535
const struct spi_mem_op *op)
536536
{
537-
struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
537+
struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller);
538538
int err = 0, i;
539539
u8 *tmpbuf;
540540

@@ -646,7 +646,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
646646
struct zynq_qspi *xqspi;
647647
u32 num_cs;
648648

649-
ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
649+
ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));
650650
if (!ctlr)
651651
return -ENOMEM;
652652

@@ -656,14 +656,14 @@ static int zynq_qspi_probe(struct platform_device *pdev)
656656
xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
657657
if (IS_ERR(xqspi->regs)) {
658658
ret = PTR_ERR(xqspi->regs);
659-
goto remove_master;
659+
goto remove_ctlr;
660660
}
661661

662662
xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
663663
if (IS_ERR(xqspi->pclk)) {
664664
dev_err(&pdev->dev, "pclk clock not found.\n");
665665
ret = PTR_ERR(xqspi->pclk);
666-
goto remove_master;
666+
goto remove_ctlr;
667667
}
668668

669669
init_completion(&xqspi->data_completion);
@@ -672,13 +672,13 @@ static int zynq_qspi_probe(struct platform_device *pdev)
672672
if (IS_ERR(xqspi->refclk)) {
673673
dev_err(&pdev->dev, "ref_clk clock not found.\n");
674674
ret = PTR_ERR(xqspi->refclk);
675-
goto remove_master;
675+
goto remove_ctlr;
676676
}
677677

678678
ret = clk_prepare_enable(xqspi->pclk);
679679
if (ret) {
680680
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
681-
goto remove_master;
681+
goto remove_ctlr;
682682
}
683683

684684
ret = clk_prepare_enable(xqspi->refclk);
@@ -724,7 +724,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
724724

725725
ret = devm_spi_register_controller(&pdev->dev, ctlr);
726726
if (ret) {
727-
dev_err(&pdev->dev, "spi_register_master failed\n");
727+
dev_err(&pdev->dev, "devm_spi_register_controller failed\n");
728728
goto clk_dis_all;
729729
}
730730

@@ -734,7 +734,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
734734
clk_disable_unprepare(xqspi->refclk);
735735
clk_dis_pclk:
736736
clk_disable_unprepare(xqspi->pclk);
737-
remove_master:
737+
remove_ctlr:
738738
spi_controller_put(ctlr);
739739

740740
return ret;

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