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Fabrizio Castrogregkh
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arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
[ Upstream commit a3f3465 ] The HW user manual for the Renesas RZ/V2H(P) SoC (a.k.a r9a09g057) states that only WDT1 is supposed to be accessed by the CA55 cores. WDT0 is supposed to be used by the CM33 core, WDT2 is supposed to be used by the CR8 core 0, and WDT3 is supposed to be used by the CR8 core 1. Remove wdt{0,2,3} from the SoC specific device tree to make it compliant with the specification from the HW manual. This change is harmless as there are currently no users of the wdt{0,2,3} device tree nodes, only the wdt1 node is actually used. Fixes: 0951054 ("arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203124247.7320-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
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arch/arm64/boot/dts/renesas/r9a09g057.dtsi

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@@ -201,16 +201,6 @@
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status = "disabled";
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};
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wdt0: watchdog@11c00400 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x11c00400 0 0x400>;
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clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
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clock-names = "pclk", "oscclk";
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resets = <&cpg 0x75>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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wdt1: watchdog@14400000 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x14400000 0 0x400>;
@@ -221,26 +211,6 @@
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status = "disabled";
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};
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wdt2: watchdog@13000000 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x13000000 0 0x400>;
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clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
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clock-names = "pclk", "oscclk";
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resets = <&cpg 0x77>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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wdt3: watchdog@13000400 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x13000400 0 0x400>;
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clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
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clock-names = "pclk", "oscclk";
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resets = <&cpg 0x78>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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rtc: rtc@11c00800 {
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compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
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reg = <0 0x11c00800 0 0x400>;

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