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ukleinekgregkh
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pwm: mediatek: Fix duty and period setting
commit f21d136 upstream. The period generated by the hardware is (PWMDWIDTH + 1) << CLKDIV) / freq according to my tests with a signal analyser and also the documentation. The current algorithm doesn't consider the `+ 1` part and so configures slightly too high periods. The same issue exists for the duty cycle setting. So subtract 1 from both the register values for period and duty cycle. If period is 0, bail out, if duty_cycle is 0, just disable the PWM which results in a constant low output. Fixes: caf065f ("pwm: Add MediaTek PWM support") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/6d1fa87a76f8020bfe3171529b8e19baffceab10.1753717973.git.u.kleine-koenig@baylibre.com Cc: stable@vger.kernel.org Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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drivers/pwm/pwm-mediatek.c

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
164164
do_div(resolution, clk_rate);
165165

166166
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
167-
while (cnt_period > 8191) {
167+
if (!cnt_period)
168+
return -EINVAL;
169+
170+
while (cnt_period > 8192) {
168171
resolution *= 2;
169172
clkdiv++;
170173
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
@@ -187,9 +190,16 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
187190
}
188191

189192
cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
193+
190194
pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
191-
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
192-
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
195+
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
196+
197+
if (cnt_duty) {
198+
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1);
199+
pwm_mediatek_enable(chip, pwm);
200+
} else {
201+
pwm_mediatek_disable(chip, pwm);
202+
}
193203

194204
out:
195205
pwm_mediatek_clk_disable(chip, pwm);
@@ -218,11 +228,8 @@ static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
218228
if (err)
219229
return err;
220230

221-
if (!pwm->state.enabled) {
231+
if (!pwm->state.enabled)
222232
err = pwm_mediatek_clk_enable(chip, pwm);
223-
if (!err)
224-
pwm_mediatek_enable(chip, pwm);
225-
}
226233

227234
return err;
228235
}

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