always @(posedge curiosity) begin
if (problem_found) begin
design_solution();
verify_thoroughly();
optimize_for_performance();
end
end- 🎓 Graduate in Embedded Systems Engineering @ INPT (June 2025)
- 🔬 Previously @ Siemens EDA (Low-Power ASIC Design)
- 🏆 Orange Summer Challenge 2024 Winner
- ⚡ Building: RISC-V processors, CNN accelerators, Custom IP cores
Hardware: SystemVerilog · Verilog · VHDL · UVM
Tools: Vivado · Quartus · ModelSim · Design Compiler · PowerPro
Languages: Python · C/C++ · Tcl · Assembly
Protocols: AXI · AMBA · I2C · SPI · UART
|
🖥️ RISC-V Processor |
🧠 CNN Accelerator |
|
⚡ SPEF Profiler |
🔌 I2C Master IP |
|
💼 Freelance FPGA/ASIC Projects on Upwork |
|
