IA32_APIC_BASE misemulated

[teisenbe]

Currently you folks seem to emulate it with

        case IA32_APIC_BASE: {
            *val = default_mem_addr;
            break;
        }

This does not deal with the bitflags in the low 12 bits of the register. In particular, there's the BSP flag (bit 8), which should read 1 on the bootstrap CPU

[raphaelning]

You're right. The IA32_APIC_BASE MSR is described in detail in the IA SDM Vol. 3A section 10.4.4 Local APIC Status and Location. There are multiple issues with HAXM's virtualization of this MSR, but we can fix the initial BSP flag first.

Please feel free to contribute a patch if you want to see this fixed soon :) We are a small team and don't have the bandwidth to get every issue closed as quickly as people would like to see...

[XevenQC]

There is no Guest OS that we tested will read/write this MSR. And this issue is gone when APIC virtualization is implemented in HAXM. So please close this issue right now and reopened if you can get some actual issues when runing Guest with HAXM.

[raggi]

@XevenQC zircon reads this msr

[SevenQC]

@raggi Could you please provide the test steps how to reprocude it?