Is AVX512 used in CRC32C acceleration?

[Nugine]

I see this news: https://www.phoronix.com/news/CRC32C-Faster-Linux-6.17

Does ISA-L have similar acceleration?

[jeffareid]

https://github.com/intel/isa-l/blob/master/crc/crc32_iscsi_by16_10.asm

One issue is the constants rk1 to rk20 are not commented and the program to generate the constants is not included in the source files. The constants are powers of 2 modulo the CRC polynomial. In this case, the instruction CRC32 is used for the final step. Although the instruction name is CRC32, it calculates CRC32C. For the other 32 bit CRCs, Barrett reduction is used:

https://github.com/intel/isa-l/blob/master/crc/crc32_ieee_by16_10.asm

When Barrett reduction is used, one of the constants is 2^64 / CRC polynomial.

I converted the older xmm based nasm code to masm code, commented the rk constants and included the code to generate the constants for using XMM registers. I just got a "renewed" laptop with AVX512 | GFNI, and will do something similar, but I'll keep the code as nasm this time.

https://github.com/jeffareid/crc/blob/master/crc32f/crc32fa.asm

https://github.com/jeffareid/crc/blob/master/crc32f/crc32fg.cpp

The ZMM code folds 256 bytes at at time, while the XMM code folds 128 bytes at a time. My guess is that folding 512 bytes at a time did not improve performance, or that there was some issue I'm not aware of.

[jeffareid]

I added 64 bit CRC AVX512 examples to my CRC directory. The constants are commented, and a program to generate the constants is included. Unlike my other examples in CRC that used MASM, these use NASM assembler with Visual Studio 2022.

https://github.com/jeffareid/crc/tree/master/crz64f

https://github.com/jeffareid/crc/tree/master/crz64r