It seems like ports 10 and 11 are swapped in the names of the uop dispatch counters. Specifically, it seems like uops_dispatched:port_2_3_10 should actually be uops_dispatched:port_2_3_11 and uops_dispatched:port_5_11 should actually be uops_dispatched:port_5_10. This is based on observations in the optimization reference manual, where ports 2,3, and 11 are grouped together because they are all AGU/LOAD:

This is backed up by information from the Intel Architecture Day slides where ports 2,3, and 11 all perform AGU/LOAD while ports 5 and 10 are ALU/LEA.


This was originally noticed in llvm/llvm-project#113847.