The Hardisc is a 32-bit RISC-V IP core for application in harsh environments, where phenomenons like random bit-flips caused by the soft errors are a concern. It contains an in-order 6-stage pipeline with AMBA 3 AHB-Lite instruction/data bus interfaces. The protection is based on a selective replication of resources in the pipeline with a focus on high operational frequency and low area and power consumption.
The development of the Hardisc is part of the research effort to provide reliable and efficient CPUs for automotive and space applications. Please consider citing the following research papers in your publications.
- In-Pipeline Processor Protection against Soft Errors - Article
- On-Chip Bus Protection against Soft Errors - Review
- Integrating Data Protection at Interface of RISC-V Processor Core
- Interface Protection Against Transient Faults
Refer to the Wiki pages for a detailed explanation of the architecture, examples, and more.
The Hardisc was tested with the riscv-dv random instruction generator, and the log files were compared with the RISC-V Spike golden model. The verification environment and scripts will be added to the repository soon.
We highly appreciate your intention to improve the Hardisc. If you want to contribute, create your branch to commit your changes and open a Pull Request. If you have questions about the architecture or want to discuss improvements, please create a new thread in the Discussions tab.
If you find any bug or a hole in the protection (also considered a bug), please create a new Issue report.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).