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Add riscv64 support #89
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Please explain the above. What do you mean by "for capacities reason"? Why change
Why "almost all"? This comment should probably be updated in your PR: |
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Hi,
The 'capacities' means that my new added feature should apply to all the riscv develop boards.
The -mabi flag is used to specify 32bit or 64 bit elf, yes, it is better to be specified for riscv64 -mabi=explicitly. The -march=native or -mtune=native can't be user for riscv64 machine neither. The -march=rv64g means "RV64IMAFD: RISC-V 64-bit Integer, Multiply and divide, Atomic, Floating point Currently the -mtune flags takes no effection. It should be omitted.You can have a quick look at [1].
The [1] https://www.sifive.com/blog/all-aboard-part-1-compiler-args |
'-mabi=lp64d’ means that ‘long’ and pointers are 64-bit (implicitly defining ‘int’ to be 32-bit), and that floating-point values up to 64 bits wide are passed in F registers. [1] https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
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Thank you for providing additional details. As you noted, RISC-V was not previously supported in unixbench, and gcc does not currently support some flag values, e.g. "native", for -march and -mtune on RISC-V Please review the suggested code block in my earlier post. |
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Hi, @gstrauss
Thanks for your words. but could you please supply more details about your earlier post, I failed to find a Pull Request template. |
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In the comment above: #89 (comment) I suggested a different structure to the code change, and I suggested updating the comment to remove the wording which says that RISC-V is not supported. |
Hi, @gstrauss I refactored my commit message,and pushed again, please help review the modification. If you need ssh to riscv64 lab environment , I would try to help you. |
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It appears that you have overlooked the code in my comment multiple times I will amend the PR. |
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With modern version control, editing the outdated changelog is extraneous, so I excluded that from your patch. Thank you for your contribution. |
'-mabi=lp64d’ means that ‘long’ and pointers are 64-bit (implicitly defining ‘int’ to be 32-bit), and that floating-point values up to 64 bits wide are passed in F registers. [1] https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html Co-authored-by: Glenn Strauss <gstrauss@gluelogic.com> github: closes #89
You are welcome! Sorry, I did forget to look at your code more carefully .🙂 Yes, your conditional logic is more clear, thanks for your refactor! |
#75 solved
GCC for riscv64 currently support -march,-mabi,-mcpu ,-mtune, -march=riscv64g can be used for almost all the riscv64 machines. I think the latter three flags should be omitted for capacities reason.
The modified source code are tested on x86(wsl2 Ubuntu20.04), aarch64(NanoPC-T4), riscv64 dev board(Nezha D1 and Sifive Unmatched) and riscv64 qemu environment.
ARCH := $(shell uname -p)was modified to
ARCH := $(shell uname -m)I'm not sure if this modification would have negative effect.
This PR can not be applied to riscv32 platform.