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Kevin Henderson edited this page Jul 1, 2026 · 9 revisions

clearCore

clearCore is an educational MIPS CPU emulator built in C++20. It makes processor internals visible and interactive — useful for students learning computer architecture or anyone who wants to see what actually happens inside a CPU.

The project ships two interfaces over identical core logic: a lightweight terminal UI (FTXUI) and a full Qt6 desktop GUI. Both let you step through instructions, watch the pipeline fill and drain, and inspect every register and memory word at each cycle.

What it does

  • Number system conversion — real-time binary / hexadecimal / decimal conversion backed by a single uint64_t value
  • MIPS instruction decoder — enter any 32-bit word and see opcode, register fields, and reconstructed assembly text
  • Single-cycle CPU — classic non-pipelined datapath; one instruction from fetch to writeback per clock
  • 5-stage pipelined CPU — concurrent IF/ID/EX/MEM/WB execution with load-use stall detection, EX/MEM and MEM/WB forwarding, and branch/jump flush handling
  • Live hazard visualization — stall, forward, and flush badges inline in the pipeline strip
  • Telemetry — running cycle count, CPI, stall/forward/flush tallies

Quick navigation

Page Description
Getting Started Build instructions, dependencies, first run
Architecture Module layout, IProcessor interface, design pillars
MIPS CPU Emulator Pipeline stages, hazard detection, forwarding
Terminal UI FTXUI interface — tabs, controls, visualizations
Qt6 GUI Desktop interface — views, signal flow, thread safety
Roadmap Stage-by-stage feature status and upcoming work
Contributing Code style, testing conventions, PR workflow

At a glance

C++20 · CMake 3.20+ · MIT license
FTXUI v7.0.0 (auto-fetched) · Qt6 (optional)
95/95 tests passing

Topics: emulator cpu mips cpp cpp20 educational computer-architecture terminal-ui

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