Verilog-Practice

There are some HDLBits website practices.And all of them have been verified.I really hope that my practices can help you to realize how Verilog works.

At the end,life is fantastic bro.

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
.DS_Store		.DS_Store
01_Step_one.v		01_Step_one.v
02_Zero.v		02_Zero.v
03_Wire.v		03_Wire.v
04_Wire4.v		04_Wire4.v
05_Inverter.v		05_Inverter.v
06_Andgate.v		06_Andgate.v
07_Norgate.v		07_Norgate.v
08_Xnorgate.v		08_Xnorgate.v
09_Wire_decl.v		09_Wire_decl.v
100_Count10.v		100_Count10.v
101_Count1to10.v		101_Count1to10.v
102_Countslow.v		102_Countslow.v
103_ece241 2014 q7a.v		103_ece241 2014 q7a.v
10_7458.v		10_7458.v
11_Vector0.v		11_Vector0.v
12_7Vector1.v		12_7Vector1.v
13_Vector2.v		13_Vector2.v
14_Vectorgates.v		14_Vectorgates.v
15_Gates4.v		15_Gates4.v
161_Bugs mux2.v		161_Bugs mux2.v
162_Bugs nand3.v		162_Bugs nand3.v
163_.v		163_.v
164_Bugs addsubz.v		164_Bugs addsubz.v
165_.v		165_.v
166_.v		166_.v
167_.v		167_.v
168_.v		168_.v
169_.v		169_.v
16_Vector3.v		16_Vector3.v
170_.v		170_.v
171_.v		171_.v
172_.v		172_.v
173_.v		173_.v
174_.v		174_.v
175_.v		175_.v
176_.v		176_.v
177_.v		177_.v
178_.v		178_.v
179_.v		179_.v
17_Vectorr.v		17_Vectorr.v
180_.v		180_.v
18_Vector4.v		18_Vector4.v
19_Vector5.v		19_Vector5.v
20_Module.v		20_Module.v
21_Module_pos.v		21_Module_pos.v
22_Module_name.v		22_Module_name.v
23_Module_shift.v		23_Module_shift.v
24_Module_shift8v.v		24_Module_shift8v.v
25_Module_add.v		25_Module_add.v
26_Module_fadd.v		26_Module_fadd.v
27_Module_cseladd.v		27_Module_cseladd.v
28_Module_addsub.v		28_Module_addsub.v
29_Alwaysblock1.v		29_Alwaysblock1.v
30_Alwaysblock2.v		30_Alwaysblock2.v
31_Always if.v		31_Always if.v
32_Always if2.v		32_Always if2.v
33_Always_case.v		33_Always_case.v
34_Always_case2v.v		34_Always_case2v.v
35_Always casezv.v		35_Always casezv.v
36_Always_nolatches.v		36_Always_nolatches.v
37_Conditional.v		37_Conditional.v
38_Reduction.v		38_Reduction.v
39_Gates100.v		39_Gates100.v
40_Vector100r.v		40_Vector100r.v
41_Popcount255.v		41_Popcount255.v
42_Adder100i.v		42_Adder100i.v
43_Bcdadd100.v		43_Bcdadd100.v
44_Wire_q4h.v		44_Wire_q4h.v
45_GND_q4i.v		45_GND_q4i.v
46_NOR_q4e.v		46_NOR_q4e.v
47_Anothergate_q4f.v		47_Anothergate_q4f.v
48_TwoGates_q4g.v		48_TwoGates_q4g.v
49_Gates.v		49_Gates.v
50_7420.v		50_7420.v
51_Truthtable1.v		51_Truthtable1.v
52_Mt2015 eq2.v		52_Mt2015 eq2.v
53_Mt2015 q4a.v		53_Mt2015 q4a.v
54_.Mt2015 q4bv.v		54_.Mt2015 q4bv.v
55_Mt2015 q4.v		55_Mt2015 q4.v
56_Ringer.v		56_Ringer.v
57_ Thermostat.v		57_ Thermostat.v
58_Popcount3.v		58_Popcount3.v
59_Gates.v		59_Gates.v
60_Gatesv100.v		60_Gatesv100.v
61_Mux2to1.v		61_Mux2to1.v
62_Mux2to1v.v		62_Mux2to1v.v
63_Mux9to1v.v		63_Mux9to1v.v
64_Mux256to1.v		64_Mux256to1.v
65_Mux256to1v.v		65_Mux256to1v.v
66_Hadd.v		66_Hadd.v
67_Fadd.v		67_Fadd.v
68_Adder3.v		68_Adder3.v
69_m2014 q4j.v		69_m2014 q4j.v
70_ece241 2014 q1c.v		70_ece241 2014 q1c.v
71_Adder100.v		71_Adder100.v
72_Bcdadd4.v		72_Bcdadd4.v
73_Kmap1.v		73_Kmap1.v
74_Kmap2.v		74_Kmap2.v
75_Kmap3.v		75_Kmap3.v

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