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Krsaurab49/README.md

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Hi, I'm Kumar Saurab 👋

RTL Design Engineer · Verilog HDL · FPGA · VLSI

🎓 M.Tech — Microelectronics & VLSI Technology  |  CGPA: 8.44 / 10

📍 India  |  🟢 Open to RTL / FPGA Opportunities

Portfolio LinkedIn Email Profile Views

💻 About Me

module KumarSaurab (
  input  wire  passion,
  input  wire  mtech_degree,
  output reg   rtl_engineer
);
  // Degree  : M.Tech — Microelectronics & VLSI Technology
  // CGPA    : 8.44 / 10
  // Focus   : RTL Design | FPGA Synthesis | Timing Closure
  // Tools   : Xilinx Vivado | ModelSim | XDC Constraints
  // Board   : Xilinx Artix-7 (Basys 3)
  // Status  : OPEN TO OPPORTUNITIES 🟢

  always @(*) begin
    if (passion && mtech_degree)
      rtl_engineer = 1'b1;  // Always TRUE
  end

endmodule

🛠️ Tech Stack

HDL & Languages

Verilog SystemVerilog Python TCL Git

EDA Tools & FPGA

Vivado ModelSim Artix-7 Basys3

Design Techniques

RTL FSM Pipelining Timing Booth

🚀 Featured Projects

🔲 High-Speed Hybrid Multiplier — FPGA

8×8-bit multiplier combining Booth radix-4 encoding with a Carry-Select / Carry-Lookahead hybrid adder tree. Synthesized and validated on Xilinx Artix-7 (Basys 3).

134MHz +57% 312 LUTs 1024 Slack

⚙️ 4-bit ALU — Verilog

Full ALU supporting 6 arithmetic and logical operations with optimized logic paths and complete testbench coverage.

100MHz 6 Ops Artix-7

🚦 Traffic Light FSM Controller

Mealy/Moore hybrid FSM for a 4-way traffic intersection, implemented and validated on FPGA with full state-transition verification.

FSM 4-way Basys3

📊 GitHub Stats

Kumar's GitHub Stats

Top Languages

🏆 Key Results

╔══════════════════════╦══════════════════════════════════════╗
║  Max Frequency       ║  134 MHz  (+57% vs ripple-carry)    ║
║  LUT Utilisation     ║  312 LUTs (12% of Artix-7)          ║
║  Setup Slack         ║  +0.3 ns  (zero violations)         ║
║  Test Coverage       ║  1,024 vectors — 100% PASS          ║
║  Degree              ║  M.Tech VLSI · CGPA 8.44            ║
╚══════════════════════╩══════════════════════════════════════╝

📬 Get In Touch

"Design without verification is guesswork."

Pinned Loading

  1. 4bit-alu-verilog 4bit-alu-verilog Public

    4-bit ALU in Verilog — 6 operations, 100 MHz on Artix-7 FPGA

    Verilog

  2. hybrid-multiplier-fpga hybrid-multiplier-fpga Public

    High-speed hybrid multiplier in Verilog — 134 MHz on Artix-7 FPGA

    Verilog 1

  3. traffic-light-fsm-verilog traffic-light-fsm-verilog Public

    4-way traffic light FSM in Verilog — Mealy/Moore hybrid on Basys 3

    Verilog 1