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KVM: nSVM: Avoid incorrect injection of SVM_EXIT_CR0_SEL_WRITE
When emulating L2 instructions, svm_check_intercept() checks whether a write to CR0 should trigger a synthesized #VMEXIT with SVM_EXIT_CR0_SEL_WRITE. However, it does not check whether L1 enabled the intercept for SVM_EXIT_WRITE_CR0, which has higher priority according to the APM (24593—Rev. 3.42—March 2024, Table 15-7): When both selective and non-selective CR0-write intercepts are active at the same time, the non-selective intercept takes priority. With respect to exceptions, the priority of this intercept is the same as the generic CR0-write intercept. Make sure L1 does NOT intercept SVM_EXIT_WRITE_CR0 before checking if SVM_EXIT_CR0_SEL_WRITE needs to be injected. Opportunistically tweak the "not CR0" logic to explicitly bail early so that it's more obvious that only CR0 has a selective intercept, and that modifying icpt_info.exit_code is functionally necessary so that the call to nested_svm_exit_handled() checks the correct exit code. Fixes: cfec82c ("KVM: SVM: Add intercept check for emulated cr accesses") Cc: stable@vger.kernel.org Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev> Link: https://patch.msgid.link/20251024192918.3191141-4-yosry.ahmed@linux.dev [sean: isolate non-CR0 write logic, tweak comments accordingly] Signed-off-by: Sean Christopherson <seanjc@google.com>
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arch/x86/kvm/svm/svm.c

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4535,15 +4535,29 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu,
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case SVM_EXIT_WRITE_CR0: {
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unsigned long cr0, val;
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4538-
if (info->intercept == x86_intercept_cr_write)
4538+
/*
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* Adjust the exit code accordingly if a CR other than CR0 is
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* being written, and skip straight to the common handling as
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* only CR0 has an additional selective intercept.
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*/
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if (info->intercept == x86_intercept_cr_write && info->modrm_reg) {
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icpt_info.exit_code += info->modrm_reg;
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break;
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}
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4541-
if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4542-
info->intercept == x86_intercept_clts)
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/*
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* Convert the exit_code to SVM_EXIT_CR0_SEL_WRITE if a
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* selective CR0 intercept is triggered (the common logic will
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* treat the selective intercept as being enabled). Note, the
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* unconditional intercept has higher priority, i.e. this is
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* only relevant if *only* the selective intercept is enabled.
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*/
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if (vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_CR0_WRITE) ||
4556+
!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0)))
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break;
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4545-
if (!(vmcb12_is_intercept(&svm->nested.ctl,
4546-
INTERCEPT_SELECTIVE_CR0)))
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/* CLTS never triggers INTERCEPT_SELECTIVE_CR0 */
4560+
if (info->intercept == x86_intercept_clts)
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break;
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/* LMSW always triggers INTERCEPT_SELECTIVE_CR0 */

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