GitHub - labanh/Verilog-HDL-Module: 2021年6月-华中科技大学-人工智能与自动化学院-数字电路Verilog语言仿真

labanh / Verilog-HDL-Module Public

2021年6月-华中科技大学-人工智能与自动化学院-数字电路Verilog语言仿真

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Name		Name	Last commit message	Last commit date
Latest commit History 30 Commits
MUX16_1.v		MUX16_1.v
MUX16_1_test.v		MUX16_1_test.v
_74HC151.v		_74HC151.v
_74HC151_test.v		_74HC151_test.v
_74HC194.v		_74HC194.v
_74HC194_test.v		_74HC194_test.v
_74HC283.v		_74HC283.v
_74HC283_test.v		_74HC283_test.v
_74HC4511.v		_74HC4511.v
_74HC4511_test.v		_74HC4511_test.v
_74HC85.v		_74HC85.v
_74HC85_test.v		_74HC85_test.v
_74LVC161.v		_74LVC161.v
_74LVC161_test.v		_74LVC161_test.v
_74X138.v		_74X138.v
_74X138_test.v		_74X138_test.v
_CD4532.v		_CD4532.v
_CD4532_test.v		_CD4532_test.v
basketball_24s.v		basketball_24s.v
basketball_24s_test.v		basketball_24s_test.v
comparator_16b.v		comparator_16b.v
comparator_16b_test.v		comparator_16b_test.v
decoder5_32.v		decoder5_32.v
decoder5_32_test.v		decoder5_32_test.v
encoder16_4.v		encoder16_4.v
encoder16_4_test.v		encoder16_4_test.v