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This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

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Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
Verilog Files		Verilog Files
Project on UART Implementation.pdf		Project on UART Implementation.pdf
README.md		README.md
SEM 3 labs on Quartus Prime and FPGA.PDF		SEM 3 labs on Quartus Prime and FPGA.PDF
UART_Report.pdf		UART_Report.pdf

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UART Implementation in FPGA

This is a group assignment done under the semester 4 module EN2111:Electronic Circuit Design.

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This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga verilog uart quartus-prime

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