4G_SDRAM

[wdxiaobai]

Hello,I used the bct what you offered and other,but the SDRAM can not update 4G_SDRAM
here are the log about tk1
sorry my English is not better.
U-Boot 2015.04 (Sep 29 2016 - 22:55:33)

TEGRA124
DRAM: 4 GiB
MMC: Tegra SD/MMC: 0, Tegra SD/MMC: 1, Tegra SD/MMC: 2
tegra-pcie: PCI regions:
tegra-pcie: I/O: 0x12000000-0x12010000
tegra-pcie: non-prefetchable memory: 0x13000000-0x20000000
tegra-pcie: prefetchable memory: 0x20000000-0x40000000
tegra-pcie: 2x1, 1x1 configuration
tegra-pcie: probing port 1, using 1 lanes
In: serial
Out: serial
Err: serial
Model: Toradex Apalis TK1 2GB V1.0B, Serial# 02822954
Net: e1000: no NVM
e1000#0
Hit any key to stop autoboot: 1 0
Booting from internal eMMC chip...
reading tegra124-apalis-eval.dtb
49196 bytes read in 19 ms (2.5 MiB/s)
reading uImage
6266384 bytes read in 157 ms (38.1 MiB/s)

Booting kernel from Legacy Image at 81000000 ...

Image Name: Angstrom/3.10.40+gitr0e41a93380f
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 6266320 Bytes = 6 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK

Flattened Device Tree blob at 82000000

Booting using the fdt blob at 0x82000000
Loading Kernel Image ... OK
Using Device Tree in place at 82000000, end 8200f02b

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 3.10.40-V2.6.1b1+g0e41a93 (linuxdev@linuxdev.toradex.int) (gcc version 5.2.1 20151005 (Linaro GCC 5.2-2015.11-2) ) #1 SMP PREEMPT Thu Sep 29 22:57:04 CEST 2016
[ 0.000000] CPU: ARMv7 Processor [413fc0f3] revision 3 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] Machine: apalis-tk1, model: Toradex Apalis TK1, serial: 0
[ 0.000000] Truncating memory at 0x80000000 to fit in 32-bit physical address space
[ 0.000000] Tegra reserved memory:
[ 0.000000] LP0: f46ff000 - f46ff80f
[ 0.000000] Bootloader framebuffer: 00000000 - 00000000
[ 0.000000] Bootloader framebuffer2: 00000000 - 00000000
[ 0.000000] Framebuffer: fa5ff000 - fb7fefff
[ 0.000000] 2nd Framebuffer: fb7ff000 - ffffefff
[ 0.000000] Carveout: 00000000 - 00000000
[ 0.000000] Vpr: 00000000 - 00000000
[ 0.000000] Tsec: 00000000 - 00000000
[ 0.000000] cma: CMA: reserved 16 MiB at ae800000
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] DTS File Name: /build/linuxdev/oe-core_V2.6.1/build/tmp-glibc/work-shared/apalis-tk1/kernel-source/arch/arm/boot/dts/tegra124-apalis-eval.dts
[ 0.000000] Tegra12: CPU Speedo value 2255, Soc Speedo value 2180, Gpu Speedo value 2016
[ 0.000000] Tegra12: CPU Speedo ID 5, Soc Speedo ID 0, Gpu Speedo ID 1
[ 0.000000] Tegra12: CPU Process ID 0,Soc Process ID 1,Gpu Process ID 0
[ 0.000000] Tegra Revision: A01 SKU: 0x87 CPU Process: 0 Core Process: 1
[ 0.000000] tegra: PLLP fixed rate: 408000000
[ 0.000000] tegra_clk_shared_bus_user_init: c2bus client se left ON
[ 0.000000] tegra_clk_shared_bus_user_init: c4bus client vi left ON
[ 0.000000] Lowering cpu_lp maximum rate from 1350000000 to 1044000000
[ 0.000000] Lowering sbus maximum rate from 420000000 to 372000000
[ 0.000000] Lowering vic03 maximum rate from 900000000 to 756000000
[ 0.000000] Lowering tsec maximum rate from 900000000 to 756000000
[ 0.000000] Lowering msenc maximum rate from 600000000 to 480000000
[ 0.000000] Lowering se maximum rate from 600000000 to 480000000
[ 0.000000] Lowering vde maximum rate from 600000000 to 480000000
[ 0.000000] Lowering host1x maximum rate from 500000000 to 408000000
[ 0.000000] Lowering vi maximum rate from 700000000 to 600000000
[ 0.000000] Lowering isp maximum rate from 700000000 to 600000000
[ 0.000000] Lowering c4bus maximum rate from 700000000 to 600000000
[ 0.000000] Lowering pll_c maximum rate from 1400000000 to 1066000000
[ 0.000000] Lowering pll_c2 maximum rate from 1200000000 to 1066000000
[ 0.000000] Lowering pll_c3 maximum rate from 1200000000 to 1066000000
[ 0.000000] Lowering hdmi maximum rate from 594000000 to 297000000
[ 0.000000] Lowering sdmmc1 maximum rate from 208000000 to 204000000
[ 0.000000] Lowering sdmmc3 maximum rate from 208000000 to 204000000
[ 0.000000] Lowering gbus maximum rate from 1032000000 to 852000000
[ 0.000000] Lowering cpu_g maximum rate from 3000000000 to 2065500000
[ 0.000000] tegra dvfs: VDD_CPU nominal 1260mV, scaling enabled
[ 0.000000] tegra dvfs: VDD_CORE nominal 1150mV, scaling enabled
[ 0.000000] tegra dvfs: VDD_GPU nominal 1200mV, scaling enabled
[ 0.000000] Switching to timer-based delay loop
[ 0.000000] tegra_powergate_init: DONE
[ 0.000000] tegra12_plle_clk_enable: pll_e is already enabled
[ 0.000000] PERCPU: Embedded 9 pages/cpu @c1e2d000 s15168 r8192 d13504 u36864
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 499215
[ 0.000000] Kernel command line: lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 ip=off root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait igb_mac=00:14:2d:2b:13:2a consoleblank=0 no_console_suspend=1 console=tty1 console=ttyS0,115200n8 debug_uartport=lsport,0 video=tegrafb0:640x480-16@60 fbcon=map:1
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 1955MB = 1955MB total
[ 0.000000] Memory: 1954560k/1954560k available, 142588k reserved, 1224696K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0b857e0 (11766 kB)
[ 0.000000] .init : 0xc0b86000 - 0xc0c04b40 ( 507 kB)
[ 0.000000] .data : 0xc0c06000 - 0xc0d5eb98 (1379 kB)
[ 0.000000] .bss : 0xc0d5eb98 - 0xc0dfc8f4 ( 632 kB)

[lgeek]

Your setup looks very different from mine (different board, different bootloader, different kernel tree, different command line arguments, etc), so it's a bit difficult to guess what's going on. Since your bootloader prints DRAM: 4 GiB, I think the BCT is working just fine and you only need to configure your kernel to use all of the memory. Have you enabled LPAE?

My bootloader passes these arguments to Linux mem=1862M@2048M mem=2048M@4096M to tell it about the address and size of RAM but you don't seem to have them. Try to append something like that manually or try to modify the DT.

Does the machine finish booting up?

[wdxiaobai]

thanks for your reply!
This it,I used different board and is tordex-apalis-tk1,I refer to your configuration in jetson-tk1, and as you said, the main problem is the kernel now.Before compiling, I wrote the kernel command line at jetson-tk1.extlinux.Conf.Emmc,but The log doesn't print out, I can't make sure it's useful, Next I will test whether the kernel command line is actually applied.

About enabled LPAE(CONFIG_ARM_LPAE=y),once I've enabled LPAE,the kernel cannot run, conversely,the machine finish booting up.

In the DT,I see that

Whether to change directly here or to the kernel command line that you mentioned above.

I don't know much about the kernel and just graduated this year. It's still difficult for me now.so thank you very much for your answer, and I'll learn more about the kernel memory architecture with your help.

[lgeek]

You definitely need LPAE, otherwise the kernel won't be able to address the top 2 GB of RAM. I have no idea why your kernel fails too boot though. Does earlyprintk get it to print something?

[wdxiaobai]

The provider will provide a version that supports LPAE,I will try again.For the early printk that you said, I haven't set it in the configuration, and I will reply here when there is a result

[wdxiaobai]

Hello！
After a period of testing the biggest problem is BCT file.But for my current information, the configuration of some registers inside the BCT file is hidden.Can you ask if you have a software reference manual for Tegra K1 (with detailed register configuration instructions)? If you can send me a copy of it? thank you!My personal email address is wdswacg@gmail.com

[lgeek]

I only have the public TRM. It documents some of the BCT-configured registers but not all, if I remember correctly. You can get a copy here.

[wdxiaobai]

TK1.log
Here is a log about kernel that have some questions,I hope you can give me some suggestion.
Thanks!