[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.

Summary of changes:
- added description of MTBUF instructions and format modifier;
- described limitations of f16 inline constants when used with integer operands;
- updated description of gfx9+ flat global addressing modes;
- v_accvgpr_write_b32 src0 corrections (gfx908);
- minor bugfixing and improvements.

Author: dpreobra

llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst

@@ -71,8 +71,8 @@ VOP3P
     **INSTRUCTION**                    **DST**       **SRC0**        **SRC1**        **SRC2**           **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     v_dot2_f32_f16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`f16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`f16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`f32<amdgpu_synid1011_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_2>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_3>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_2>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_3>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i8x4<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i8x4<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`u8x4<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`u8x4<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i4x8<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i4x8<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -87,6 +87,8 @@ VOP3P
     AMDGPUAsmGFX10
     gfx1011_src32_0
     gfx1011_src32_1
+    gfx1011_src32_2
+    gfx1011_src32_3
     gfx1011_vdst32_0
     gfx1011_vsrc32_0
     gfx1011_type_dev

llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst

@@ -64,8 +64,8 @@ VOP3P
     **INSTRUCTION**                    **DST**       **SRC0**        **SRC1**        **SRC2**           **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     v_dot2_f32_f16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`f16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`f16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`f32<amdgpu_synid906_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_3>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_4>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_3>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_4>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i8x4<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i8x4<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`u8x4<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`u8x4<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i4x8<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i4x8<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -84,6 +84,8 @@ VOP3P
     gfx906_src32_0
     gfx906_src32_1
     gfx906_src32_2
+    gfx906_src32_3
+    gfx906_src32_4
     gfx906_vdst32_0
     gfx906_vsrc32_0
     gfx906_mad_type_dev

llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst

@@ -95,8 +95,8 @@ VOP3P
     v_accvgpr_read_b32     :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`asrc<amdgpu_synid908_asrc32_0>`
     v_accvgpr_write_b32    :ref:`adst<amdgpu_synid908_adst32_0>`,        :ref:`src<amdgpu_synid908_src32_3>`
     v_dot2_f32_f16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`f16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`f16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`f32<amdgpu_synid908_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_4>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_5>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_4>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_5>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i8x4<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i8x4<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`u8x4<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`u8x4<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i4x8<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i4x8<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -150,6 +150,8 @@ VOP3P
     gfx908_src32_1
     gfx908_src32_2
     gfx908_src32_3
+    gfx908_src32_4
+    gfx908_src32_5
     gfx908_vaddr_flat_global
     gfx908_vasrc32_0
     gfx908_vasrc64_0

llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid1011_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid1011_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst

@@ -17,7 +17,7 @@ This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_syn
 *Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
 
 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_vcc_lo>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
 
 
 *Operands:* :ref:`v<amdgpu_synid_v>`