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[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes: - added description of GFX90A; - minor bugfixing and improvements.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst‎

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‎llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst‎

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soffset
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===========================
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An unsigned byte offset added to the base address to get memory address.
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.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
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An unsigned 20-bit offset added to the base address to get memory address.
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*Size:* 1 dword.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`

‎llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst‎

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* If offset is specified as a register, it supplies an unsigned byte offset.
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* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
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.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
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*Size:* 1 dword.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`

‎llvm/docs/AMDGPU/gfx90a_dst.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_dst:
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dst
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===
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This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

‎llvm/docs/AMDGPU/gfx90a_fx_operand.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_fx_operand:
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FX Operand
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==========
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This is an *f32* or *f16* operand depending on instruction modifiers:
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* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.

‎llvm/docs/AMDGPU/gfx90a_hwreg.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_hwreg:
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hwreg
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=====
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Bits of a hardware register being accessed.
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The bits of this operand have the following meaning:
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======= ===================== ============
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Bits Description Value Range
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======= ===================== ============
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5:0 Register *id*. 0..63
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10:6 First bit *offset*. 0..31
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15:11 *Size* in bits. 1..32
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======= ===================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* An *hwreg* value described below.
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==================================== ============================================================================
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Hwreg Value Syntax Description
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==================================== ============================================================================
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hwreg({0..63}) All bits of a register indicated by its *id*.
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hwreg(<*name*>) All bits of a register indicated by its *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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==================================== ============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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=================== ==========================================
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Name Description
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=================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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=================== ==========================================
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Examples:
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.. parsed-literal::
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reg = 1
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offset = 2
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size = 4
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hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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s_getreg_b32 s2, 0x1881
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s_getreg_b32 s2, hwreg_enc // the same as above
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s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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s_getreg_b32 s2, hwreg(15)
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s_getreg_b32 s2, hwreg(51, 1, 31)
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s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

‎llvm/docs/AMDGPU/gfx90a_imask.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imask:
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imask
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=====
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This operand is a mask which controls indexing mode for operands of subsequent instructions.
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Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
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Value 1 enables indexing and value 0 disables it.
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===== ========================================
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Bit Meaning
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===== ========================================
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0 Enables or disables *src0* indexing.
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1 Enables or disables *src1* indexing.
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2 Enables or disables *src2* indexing.
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3 Enables or disables *dst* indexing.
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===== ========================================
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
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* A *gpr_idx* value described below.
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==================================== ===========================================
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Gpr_idx Value Syntax Description
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==================================== ===========================================
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gpr_idx(*<operands>*) Enable indexing for specified *operands*
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and disable it for the rest.
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*Operands* is a comma-separated list of
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values which may include:
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* "SRC0" - enable *src0* indexing.
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* "SRC1" - enable *src1* indexing.
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* "SRC2" - enable *src2* indexing.
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* "DST" - enable *dst* indexing.
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Each of these values may be specified only
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once.
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*Operands* list may be empty; this syntax
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disables indexing for all operands.
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==================================== ===========================================
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Examples:
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.. parsed-literal::
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s_set_gpr_idx_mode 0
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s_set_gpr_idx_mode gpr_idx() // the same as above
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s_set_gpr_idx_mode 15
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s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
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s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
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s_set_gpr_idx_mode gpr_idx(DST,SRC1)

‎llvm/docs/AMDGPU/gfx90a_imm16.rst‎

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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

‎llvm/docs/AMDGPU/gfx90a_imm16_1.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_1:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

‎llvm/docs/AMDGPU/gfx90a_imm16_2.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_2:
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imm16
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=====
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A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

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