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[AMDGPU][GFX11][DOC][NFC] Add GFX11 assembler syntax description
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX11.rst‎

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‎llvm/docs/AMDGPU/gfx11_attr.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_attr:
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attr
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====
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Interpolation attribute and channel:
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============== ===================================
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Syntax Description
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============== ===================================
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attr{0..32}.x Attribute 0..32 with *x* channel.
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attr{0..32}.y Attribute 0..32 with *y* channel.
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attr{0..32}.z Attribute 0..32 with *z* channel.
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attr{0..32}.w Attribute 0..32 with *w* channel.
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============== ===================================
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Examples:
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.. parsed-literal::
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lds_param_load v5, attr0.z

‎llvm/docs/AMDGPU/gfx11_delay.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_delay:
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delay
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=====
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A delay between dependent SALU/VALU instructions.
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This operand may specify a delay for 2 instructions:
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the one after the current *s_delay_alu* instruction
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and for the second instruction indicated by *SKIP*.
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The bits of this operand have the following meaning:
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===== ========================================================== ============
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Bits Description Value Range
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===== ========================================================== ============
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3:0 ID0: indicates a delay for the first instruction. 0..11
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6:4 SKIP: indicates the position of the second instruction. 0..5
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10:7 ID1: indicates a delay for the second instruction. 0..11
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===== ========================================================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
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* A combination of *instid0*, *instskip*, *instid1* values which are described below.
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======================== =========================== ===============
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Syntax Description Default Value
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======================== =========================== ===============
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instid0(<*ID name*>) A symbolic *ID0* value. instid0(NO_DEP)
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instskip(<*SKIP name*>) A symbolic *SKIP* value. instskip(SAME)
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instid1(<*ID name*>) A symbolic *ID1* value. instid1(NO_DEP)
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======================== =========================== ===============
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These values may be specified in any order.
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When more than one value is specified, the values must be separated from each other by a '|'.
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Valid *ID names* are defined below.
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=================== ===================================================================
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Name Description
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=================== ===================================================================
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NO_DEP No dependency on any prior instruction. This is the default value.
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VALU_DEP_1 Dependency on a previous VALU instruction, 1 opcode back.
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VALU_DEP_2 Dependency on a previous VALU instruction, 2 opcodes back.
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VALU_DEP_3 Dependency on a previous VALU instruction, 3 opcodes back.
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VALU_DEP_4 Dependency on a previous VALU instruction, 4 opcodes back.
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TRANS32_DEP_1 Dependency on a previous TRANS32 instruction, 1 opcode back.
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TRANS32_DEP_2 Dependency on a previous TRANS32 instruction, 2 opcodes back.
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TRANS32_DEP_3 Dependency on a previous TRANS32 instruction, 3 opcodes back.
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FMA_ACCUM_CYCLE_1 Single cycle penalty for FMA accumulation.
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SALU_CYCLE_1 1 cycle penalty for a prior SALU instruction.
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SALU_CYCLE_2 2 cycle penalty for a prior SALU instruction.
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SALU_CYCLE_3 3 cycle penalty for a prior SALU instruction.
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=================== ===================================================================
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Legal *SKIP names* are described in the following table.
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======== ============================================================================
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Name Description
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======== ============================================================================
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SAME Apply second dependency to the same instruction. This is the default value.
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NEXT Apply second dependency to the next instruction.
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SKIP_1 Skip 1 instruction then apply dependency.
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SKIP_2 Skip 2 instructions then apply dependency.
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SKIP_3 Skip 3 instructions then apply dependency.
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SKIP_4 Skip 4 instructions then apply dependency.
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======== ============================================================================
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Examples:
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.. parsed-literal::
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s_delay_alu instid0(VALU_DEP_1)
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s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)

‎llvm/docs/AMDGPU/gfx11_dst.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_dst:
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dst
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===
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This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

‎llvm/docs/AMDGPU/gfx11_fx_operand.rst‎

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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_fx_operand:
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FX Operand
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==========
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This is a *f32* or *f16* operand depending on instruction modifiers:
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* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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* Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.

‎llvm/docs/AMDGPU/gfx11_hwreg.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_hwreg:
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hwreg
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=====
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Bits of a hardware register being accessed.
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The bits of this operand have the following meaning:
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======= ===================== ============
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Bits Description Value Range
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======= ===================== ============
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5:0 Register *id*. 0..63
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10:6 First bit *offset*. 0..31
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15:11 *Size* in bits. 1..32
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======= ===================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
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* An *hwreg* value which is described below.
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==================================== ===============================================================================
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Hwreg Value Syntax Description
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==================================== ===============================================================================
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hwreg({0..63}) All bits of a register indicated by the register *id*.
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hwreg(<*name*>) All bits of a register indicated by the register *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*.
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==================================== ===============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Predefined register *names* include:
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============================== ==========================================
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Name Description
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============================== ==========================================
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HW_REG_MODE Shader writable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
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HW_REG_HW_ID2 Id of queue, pipeline, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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============================== ==========================================
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Examples:
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.. parsed-literal::
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reg = 1
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offset = 2
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size = 4
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hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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s_getreg_b32 s2, 0x1881
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s_getreg_b32 s2, hwreg_enc // the same as above
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s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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s_getreg_b32 s2, hwreg(15)
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s_getreg_b32 s2, hwreg(51, 1, 31)
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s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

‎llvm/docs/AMDGPU/gfx11_imm16_0533c2.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_imm16_0533c2:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.

‎llvm/docs/AMDGPU/gfx11_imm16_169952.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_imm16_169952:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 65535.

‎llvm/docs/AMDGPU/gfx11_label.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_label:
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label
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=====
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A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
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* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
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Examples:
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.. parsed-literal::
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offset = 30
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label_1:
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label_2 = . + 4
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s_branch 32
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s_branch offset + 2
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s_branch label_1
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s_branch label_2
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s_branch label_3
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s_branch label_4
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label_3 = label_2 + 4
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label_4:

‎llvm/docs/AMDGPU/gfx11_m_181aa0.rst‎

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_m_181aa0:
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m
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=
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This operand may be used with a floating-point operand modifier :ref:`neg<amdgpu_synid_neg>`.

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