[AMDGPU][MC][DOC] Updated AMD GPU assembler description.

Summary of changes:
- Updated to reflect recent changes in assembler;
- Minor bugfixing and improvements.

llvm-svn: 372857

Author: dpreobra

llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst

@@ -566,7 +566,7 @@ SOPC
     s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid8_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc64_0>`
     s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
     s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
-    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid8_ssrc32_0>`,     :ref:`imm4<amdgpu_synid8_imm4>`
+    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid8_ssrc32_0>`,     :ref:`imask<amdgpu_synid8_imask>`
     s_setvskip                     :ref:`ssrc0<amdgpu_synid8_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid8_ssrc32_0>`
 
 SOPK
@@ -624,7 +624,7 @@ SOPP
     s_nop                          :ref:`imm16<amdgpu_synid8_bimm16>`
     s_sendmsg                      :ref:`msg<amdgpu_synid8_msg>`
     s_sendmsghalt                  :ref:`msg<amdgpu_synid8_msg>`
-    s_set_gpr_idx_mode             :ref:`imm4<amdgpu_synid8_imm4>`
+    s_set_gpr_idx_mode             :ref:`imask<amdgpu_synid8_imask>`
     s_set_gpr_idx_off
     s_sethalt                      :ref:`imm16<amdgpu_synid8_bimm16>`
     s_setkill                      :ref:`imm16<amdgpu_synid8_bimm16>`
@@ -1756,7 +1756,7 @@ VOPC
     gfx8_fimm16
     gfx8_fimm32
     gfx8_hwreg
-    gfx8_imm4
+    gfx8_imask
     gfx8_label
     gfx8_msg
     gfx8_param

llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst

@@ -736,7 +736,7 @@ SOPC
     s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
     s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
     s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
-    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid9_ssrc32_0>`,     :ref:`imm4<amdgpu_synid9_imm4>`
+    s_set_gpr_idx_on               :ref:`ssrc<amdgpu_synid9_ssrc32_0>`,     :ref:`imask<amdgpu_synid9_imask>`
     s_setvskip                     :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
 
 SOPK
@@ -796,7 +796,7 @@ SOPP
     s_nop                          :ref:`imm16<amdgpu_synid9_bimm16>`
     s_sendmsg                      :ref:`msg<amdgpu_synid9_msg>`
     s_sendmsghalt                  :ref:`msg<amdgpu_synid9_msg>`
-    s_set_gpr_idx_mode             :ref:`imm4<amdgpu_synid9_imm4>`
+    s_set_gpr_idx_mode             :ref:`imask<amdgpu_synid9_imask>`
     s_set_gpr_idx_off
     s_sethalt                      :ref:`imm16<amdgpu_synid9_bimm16>`
     s_setkill                      :ref:`imm16<amdgpu_synid9_bimm16>`
@@ -2010,7 +2010,7 @@ VOPC
     gfx9_fimm16
     gfx9_fimm32
     gfx9_hwreg
-    gfx9_imm4
+    gfx9_imask
     gfx9_label
     gfx9_msg
     gfx9_param

llvm/docs/AMDGPU/gfx10_bimm16.rst

@@ -10,5 +10,5 @@
 imm16
 ===========================
 
-An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
 

llvm/docs/AMDGPU/gfx10_bimm32.rst

@@ -10,5 +10,5 @@
 imm32
 ===========================
 
-An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
 

llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst

@@ -21,7 +21,7 @@ Optionally may serve as an output data:
 * :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
 * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
 
-  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+  Note: the surface data format is indicated in the image resource constant but not in the instruction.
 
 
 *Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst

@@ -21,6 +21,6 @@ Optionally may serve as an output data:
 * :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
 * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
 
-  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+  Note: the surface data format is indicated in the image resource constant but not in the instruction.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx10_fimm16.rst

@@ -10,5 +10,6 @@
 imm32
 ===========================
 
-An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
 

llvm/docs/AMDGPU/gfx10_fimm32.rst

@@ -10,5 +10,6 @@
 imm32
 ===========================
 
-An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
 

llvm/docs/AMDGPU/gfx10_hwreg.rst

@@ -14,26 +14,30 @@ Bits of a hardware register being accessed.
 
 The bits of this operand have the following meaning:
 
-    ============ ===================================
-    Bits         Description
-    ============ ===================================
-    5:0          Register *id*.
-    10:6         First bit *offset* (0..31).
-    15:11        *Size* in bits (1..32).
-    ============ ===================================
+    ======= ===================== ============
+    Bits    Description           Value Range
+    ======= ===================== ============
+    5:0     Register *id*.        0..63
+    10:6    First bit *offset*.   0..31
+    15:11   *Size* in bits.       1..32
+    ======= ===================== ============
 
-This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
 
     ==================================== ============================================================================
-    Syntax                               Description
+    Hwreg Value Syntax                   Description
     ==================================== ============================================================================
     hwreg({0..63})                       All bits of a register indicated by its *id*.
     hwreg(<*name*>)                      All bits of a register indicated by its *name*.
     hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
     hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
     ==================================== ============================================================================
 
-Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
 
 Defined register *names* include:
 
@@ -62,7 +66,16 @@ Examples:
 
 .. parsed-literal::
 
-    s_getreg_b32 s2, 0x6
+    reg = 1
+    offset = 2
+    size = 4
+    hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+    s_getreg_b32 s2, 0x1881
+    s_getreg_b32 s2, hwreg_enc                     // the same as above
+    s_getreg_b32 s2, hwreg(1, 2, 4)                // the same as above
+    s_getreg_b32 s2, hwreg(reg, offset, size)      // the same as above
+
     s_getreg_b32 s2, hwreg(15)
     s_getreg_b32 s2, hwreg(51, 1, 31)
     s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

llvm/docs/AMDGPU/gfx10_label.rst

@@ -12,19 +12,26 @@ label
 
 A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
 
-This operand may be specified as:
+This operand may be specified as one of the following:
 
-* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
-* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
-* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
 
 Examples:
 
 .. parsed-literal::
 
   offset = 30
-  s_branch loop_end
-  s_branch 2 + offset
+  label_1:
+  label_2 = . + 4
+
   s_branch 32
-  loop_end:
+  s_branch offset + 2
+  s_branch label_1
+  s_branch label_2
+  s_branch label_3
+  s_branch label_4
+
+  label_3 = label_2 + 4
+  label_4: