[AMDGPU][DOC][NFC] Update assembler syntax description

Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Small improvements and clarifications.
- Correct typos.

Author: dpreobra

llvm/docs/AMDGPUInstructionNotation.rst

@@ -10,10 +10,10 @@ AMDGPU Instructions Notation
 Introduction
 ============
 
-This is an overview of notation used to describe syntax of AMDGPU assembler instructions.
+This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
 
-This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
-except that instead of real operands and modifiers it provides references to their description.
+This notation looks a lot like the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`,
+except that instead of real operands and modifiers, it uses references to their descriptions.
 
 Instructions
 ============
@@ -23,7 +23,9 @@ Notation
 
 This is the notation used to describe AMDGPU instructions:
 
-    ``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``>  <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``>  <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
+  | ``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``>
+      <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``>
+      <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
 
 .. _amdgpu_syn_opcode_notation:
 
@@ -42,7 +44,8 @@ Operands
 
 An instruction may have zero or more *operands*. They are comma-separated in the description:
 
-    ``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>, <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
+  | ``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>,
+      <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
 
 The order of *operands* is fixed. *Operands* cannot be omitted
 except for special cases described below.
@@ -60,7 +63,8 @@ Where:
 
 * *kind* is an optional prefix describing operand :ref:`kind<amdgpu_syn_instruction_operand_kinds>`.
 * *name* is a link to a description of the operand.
-* *tags* are optional. They are used to indicate :ref:`special operand properties<amdgpu_syn_instruction_operand_tags>`.
+* *tags* are optional. They are used to indicate
+  :ref:`special operand properties<amdgpu_syn_instruction_operand_tags>`.
 
 .. _amdgpu_syn_instruction_operand_kinds:
 
@@ -70,16 +74,16 @@ Operand Kinds
 Operand kind indicates which values are accepted by the operand.
 
 * Operands which only accept *vector* registers are labelled with 'v' prefix.
-* Operands which only accept *scalar* values are labelled with 's' prefix.
-* Operands which accept both *vector* registers and *scalar* values have no prefix.
+* Operands which only accept *scalar* registers and values are labelled with 's' prefix.
+* Operands which accept any registers and values have no prefix.
 
 Examples:
 
 .. parsed-literal::
 
     vdata          // operand only accepts vector registers
     sdst           // operand only accepts scalar registers
-    src1           // operand accepts both scalar and vector registers
+    src1           // operand accepts vector registers, scalar registers, and scalar values
 
 .. _amdgpu_syn_instruction_operand_tags:
 
@@ -92,16 +96,16 @@ Operand tags indicate special operand properties.
     Operand tag    Meaning
     ============== =================================================================================
     :opt           An optional operand.
-    :m             An operand which may be used with
-                   :ref:`VOP3 operand modifiers<amdgpu_synid_vop3_operand_modifiers>` or
-                   :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
-    :dst           An input operand which may also serve as a destination
+    :m             An operand which may be used with operand modifiers
+                   :ref:`abs<amdgpu_synid_abs>`, :ref:`neg<amdgpu_synid_neg>` or
+                   :ref:`sext<amdgpu_synid_sext>`.
+    :dst           An input operand which is also used as a destination
                    if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
-    :fx            This is an *f32* or *f16* operand depending on
+    :fx            This is a *f32* or *f16* operand, depending on
                    :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
-    :<type>        Operand *type* differs from *type*
+    :<type>        The operand *type* differs from the *type*
                    :ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
-                   This tag specifies actual operand *type*.
+                   This tag specifies the actual operand *type*.
     ============== =================================================================================
 
 Examples:
@@ -119,7 +123,8 @@ Modifiers
 
 An instruction may have zero or more optional *modifiers*. They are space-separated in the description:
 
-    ``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``> <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
+  | ``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``>
+      <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
 
 The order of *modifiers* is fixed.
 
@@ -132,4 +137,4 @@ A *modifier* is described using the following notation:
 
     *<name>*
 
-Where *name* is a link to a description of the *modifier*.
+Where the *name* is a link to a description of the *modifier*.

llvm/docs/AMDGPUInstructionSyntax.rst

@@ -15,9 +15,10 @@ Syntax
 
 An instruction has the following syntax:
 
-    ``<``\ *opcode mnemonic*\ ``>    <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
+  | ``<``\ *opcode mnemonic*\ ``>    <``\ *operand0*\ ``>,
+      <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
 
-:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
+:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated, while
 :doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
 
 The order of *operands* and *modifiers* is fixed.
@@ -28,7 +29,8 @@ Most *modifiers* are optional and may be omitted.
 Opcode Mnemonic
 ~~~~~~~~~~~~~~~
 
-Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:
+Opcode mnemonic describes opcode semantics
+and may include one or more suffices in this order:
 
 * :ref:`Packing suffix<amdgpu_syn_instruction_pk>`.
 * :ref:`Destination operand type suffix<amdgpu_syn_instruction_type>`.
@@ -81,7 +83,7 @@ The following table enumerates the most frequently used type suffices.
     ============================================ ======================= ============================
 
 Instructions which have no type suffices are assumed to operate with typeless data.
-The size of data is specified by size suffices:
+The size of typeless data is specified by size suffices:
 
     ================= =================== =====================================
     Size Suffix       Implied data type   Required register size in dwords
@@ -103,8 +105,8 @@ The size of data is specified by size suffices:
     ================= =================== =====================================
 
 .. WARNING::
-    There are exceptions from rules described above.
-    Operands which have type different from type specified by the opcode are
+    There are exceptions to the rules described above.
+    Operands which have a type different from the type specified by the opcode are
     :ref:`tagged<amdgpu_syn_instruction_operand_tags>` in the description.
 
 Examples of instructions with different types of source and destination operands:
@@ -144,7 +146,9 @@ Encoding Suffices
 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
 
-The assembler will automatically use optimal encoding based on instruction operands.
+The assembler selects an optimal encoding automatically
+based on instruction operands and modifiers,
+unless a specific encoding is explicitly requested.
 To force specific encoding, one can add a suffix to the opcode of the instruction:
 
     =================================================== =================
@@ -156,25 +160,26 @@ To force specific encoding, one can add a suffix to the opcode of the instructio
     *SDWA* encoding                                     _sdwa
     =================================================== =================
 
-These suffices are used in this reference to indicate the assumed encoding.
-When no suffix is specified, native instruction encoding is implied.
+This reference uses encoding suffices to specify which encoding is implied.
+When no suffix is specified, native instruction encoding is assumed.
 
 Operands
 ========
 
 Syntax
 ~~~~~~
 
-Syntax of generic operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
+The syntax of generic operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
 
-For detailed information about operands follow *operand links* in GPU-specific documents.
+For detailed information about operands, follow *operand links* in GPU-specific documents.
 
 Modifiers
 =========
 
 Syntax
 ~~~~~~
 
-Syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
+The syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
 
-Information about modifiers supported for individual instructions may be found in GPU-specific documents.
+Information about modifiers supported for individual instructions
+may be found in GPU-specific documents.