[Sim] Set the GetFileOp operation to procedural only

Author: nanjo712

include/circt/Dialect/Sim/SimOps.td

@@ -610,17 +610,22 @@ def PrintFormattedProcOp : SimOp<"proc.print", [ProceduralOp]> {
   let assemblyFormat = "$input (`to` $stream^)? attr-dict";
 }
 
-def GetFileOp : SimOp<"get_file", [Pure]> {
-  let summary = "Get an output stream for a formatted file name";
+def GetFileOp : SimOp<"get_file", [ProceduralOp]> {
+  let summary = "Create an output stream for a formatted file name";
   let description = [{
-    Resolves a file name from a `!sim.fstring` value and returns an output
-    stream resource that can be consumed by `sim.print` or `sim.proc.print`.
-    The file-name format string should be constructed using `sim.fmt.*`
-    operations, just like any other Sim format-string value.
-    The file-name format string is evaluated whenever the stream is accessed.
+    Resolves a file name from a `!sim.fstring` value, immediately creates the
+    corresponding file, and returns an output stream resource that can be
+    consumed by `sim.proc.print`. The file-name format string should be
+    constructed using `sim.fmt.*` operations, just like any other Sim
+    format-string value.
+
+    This operation has an immediate side effect: executing it creates the file,
+    even if the returned stream is never subsequently consumed.
 
     The concrete runtime representation and lifetime management of the returned
     stream are backend-defined.
+
+    This operation must be within a procedural region.
   }];
 
   let arguments = (ins FormatStringType:$fileName);

lib/Conversion/SimToSV/SimToSV.cpp

@@ -731,11 +731,37 @@ FailureOr<Value> createFileDescriptorGetterForGetFile(GetFileOp getFileOp,
 LogicalResult lowerPrintFormattedProcToSV(hw::HWModuleOp module,
                                           const TypeConverter &typeConverter,
                                           SimConversionState &state) {
+  SmallVector<GetFileOp> getFileOps;
   SmallVector<PrintFormattedProcOp> printOps;
-  module.walk([&](PrintFormattedProcOp op) { printOps.push_back(op); });
+  module.walk([&](Operation *op) {
+    if (auto getFileOp = dyn_cast<GetFileOp>(op))
+      getFileOps.push_back(getFileOp);
+    if (auto printOp = dyn_cast<PrintFormattedProcOp>(op))
+      printOps.push_back(printOp);
+  });
 
   llvm::SmallPtrSet<Operation *, 8> dceRoots;
 
+  for (auto getFileOp : getFileOps) {
+    OpBuilder builder(getFileOp);
+    auto fdOrFailure = createFileDescriptorGetterForGetFile(getFileOp, builder);
+    if (failed(fdOrFailure))
+      return failure();
+
+    auto stream = mlir::UnrealizedConversionCastOp::create(
+        builder, getFileOp.getLoc(), getFileOp.getResult().getType(),
+        *fdOrFailure);
+    getFileOp.replaceAllUsesWith(stream.getResult(0));
+    state.usedFileDescriptorRuntime = true;
+    state.usedSynthesisMacro = true;
+
+    auto *procRoot =
+        getFileOp->getParentWithTrait<mlir::OpTrait::IsIsolatedFromAbove>();
+    if (procRoot)
+      dceRoots.insert(procRoot);
+    getFileOp.erase();
+  }
+
   for (auto printOp : printOps) {
     OpBuilder builder(printOp);
     SmallString<128> formatString;
@@ -752,22 +778,11 @@ LogicalResult lowerPrintFormattedProcToSV(hw::HWModuleOp module,
       // no stream is specified, emit sv.write.
       sv::WriteOp::create(builder, printOp.getLoc(), formatString, args);
     } else {
-      Value fd;
-      if (auto getFileOp = stream.getDefiningOp<GetFileOp>()) {
-        auto fdOrFailure =
-            createFileDescriptorGetterForGetFile(getFileOp, builder);
-        if (failed(fdOrFailure))
-          return failure();
-        fd = *fdOrFailure;
-        state.usedFileDescriptorRuntime = true;
-        state.usedSynthesisMacro = true;
-      } else {
-        auto fdType = typeConverter.convertType(stream.getType());
-        assert(fdType && "expected output stream type conversion");
-        fd = mlir::UnrealizedConversionCastOp::create(builder, printOp.getLoc(),
-                                                      fdType, stream)
-                 ->getResult(0);
-      }
+      auto fdType = typeConverter.convertType(stream.getType());
+      assert(fdType && "expected output stream type conversion");
+      Value fd = mlir::UnrealizedConversionCastOp::create(
+                     builder, printOp.getLoc(), fdType, stream)
+                     ->getResult(0);
       sv::FWriteOp::create(builder, printOp.getLoc(), fd, formatString, args);
     }
     auto *procRoot =

test/Conversion/SimToSV/lower-print-formatted-proc-to-sv.mlir

@@ -173,10 +173,10 @@ hw.module @print_to_file_under_condition(in %clk : i1, in %idx : i8, in %en : i1
     scf.if %en_in {
       %msg = sim.fmt.literal "enabled"
       // CHECK: ^bb0(%[[IDX:.+]]: i8, %[[EN:.+]]: i1):
+      // CHECK-NEXT: %[[UNSIGNED:.+]] = sv.system "unsigned"(%[[IDX]]) : (i8) -> i8
+      // CHECK-NEXT: %[[FILENAME:.+]] = sv.sformatf "trace_%02d.log"(%[[UNSIGNED]]) : i8
+      // CHECK-NEXT: %[[FD:.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"(%[[FILENAME]]) : (!hw.string) -> i32
       // CHECK-NEXT: scf.if %[[EN]] {
-      // CHECK-NEXT:   %[[UNSIGNED:.+]] = sv.system "unsigned"(%[[IDX]]) : (i8) -> i8
-      // CHECK-NEXT:   %[[FILENAME:.+]] = sv.sformatf "trace_%02d.log"(%[[UNSIGNED]]) : i8
-      // CHECK-NEXT:   %[[FD:.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"(%[[FILENAME]]) : (!hw.string) -> i32
       // CHECK-NEXT:   sv.fwrite %[[FD]], "enabled"
       sim.proc.print %msg to %file
     }

test/Dialect/Sim/proceduralize-sim.mlir

@@ -282,84 +282,3 @@ hw.module @condition_as_val(in %clk: !seq.clock, in %condval: i1) {
     %bin = sim.fmt.bin %condval specifierWidth 1 : i1
     sim.print %bin on %clk if %condval
 }
-
-// CHECK-LABEL: @print_with_stream
-// CHECK-NEXT:  %[[TRG:.*]] = seq.from_clock %clk
-// CHECK-NEXT:  hw.triggered posedge %[[TRG]](%cond, %idx) : i1, i32 {
-// CHECK-NEXT:  ^bb0(%[[ARGCOND:.*]]: i1, %[[ARGIDX:.*]]: i32):
-// CHECK-DAG:     %[[FMT:.*]] = sim.fmt.literal "stream"
-// CHECK-DAG:     %[[PFX:.*]] = sim.fmt.literal "out_"
-// CHECK-DAG:     %[[NUM:.*]] = sim.fmt.dec %[[ARGIDX]] : i32
-// CHECK-DAG:     %[[SFX:.*]] = sim.fmt.literal ".log"
-// CHECK-DAG:     %[[FNAME:.*]] = sim.fmt.concat (%[[PFX]], %[[NUM]], %[[SFX]])
-// CHECK-DAG:     %[[FILE:.*]] = sim.get_file %[[FNAME]]
-// CHECK:         scf.if %[[ARGCOND]] {
-// CHECK-NEXT:      sim.proc.print %[[FMT]] to %[[FILE]]
-// CHECK-NEXT:    }
-// CHECK-NEXT:  }
-hw.module @print_with_stream(in %clk: !seq.clock, in %cond: i1, in %idx: i32) {
-  %fmt = sim.fmt.literal "stream"
-  %prefix = sim.fmt.literal "out_"
-  %idxFmt = sim.fmt.dec %idx : i32
-  %suffix = sim.fmt.literal ".log"
-  %fileName = sim.fmt.concat (%prefix, %idxFmt, %suffix)
-  %file = sim.get_file %fileName
-  sim.print %fmt on %clk if %cond to %file
-}
-
-// CHECK-LABEL: @print_with_stream_two_conditions
-// CHECK-NEXT:  %[[TRG:.*]] = seq.from_clock %clk
-// CHECK-NEXT:  hw.triggered posedge %[[TRG]](%c1, %idx, %c2) : i1, i32, i1 {
-// CHECK-NEXT:  ^bb0(%[[ARGC1:.*]]: i1, %[[ARGIDX:.*]]: i32, %[[ARGC2:.*]]: i1):
-// CHECK-DAG:     %[[FMT:.*]] = sim.fmt.literal "stream2"
-// CHECK-DAG:     %[[PFX:.*]] = sim.fmt.literal "out2_"
-// CHECK-DAG:     %[[NUM:.*]] = sim.fmt.dec %[[ARGIDX]] : i32
-// CHECK-DAG:     %[[SFX:.*]] = sim.fmt.literal ".log"
-// CHECK-DAG:     %[[FNAME:.*]] = sim.fmt.concat (%[[PFX]], %[[NUM]], %[[SFX]])
-// CHECK-DAG:     %[[FILE:.*]] = sim.get_file %[[FNAME]]
-// CHECK:         scf.if %[[ARGC1]] {
-// CHECK-NEXT:      sim.proc.print %[[FMT]] to %[[FILE]]
-// CHECK-NEXT:    }
-// CHECK-NEXT:    scf.if %[[ARGC2]] {
-// CHECK-NEXT:      sim.proc.print %[[FMT]] to %[[FILE]]
-// CHECK-NEXT:    }
-// CHECK-NEXT:  }
-hw.module @print_with_stream_two_conditions(in %clk: !seq.clock, in %c1: i1, in %c2: i1, in %idx: i32) {
-  %fmt = sim.fmt.literal "stream2"
-  %prefix = sim.fmt.literal "out2_"
-  %idxFmt = sim.fmt.dec %idx : i32
-  %suffix = sim.fmt.literal ".log"
-  %fileName = sim.fmt.concat (%prefix, %idxFmt, %suffix)
-  %file = sim.get_file %fileName
-  sim.print %fmt on %clk if %c1 to %file
-  sim.print %fmt on %clk if %c2 to %file
-}
-
-// CHECK-LABEL: @shared_fmt_between_print_and_get_file
-// CHECK-NEXT:  %[[TRG:.*]] = seq.from_clock %clk
-// CHECK-NEXT:  hw.triggered posedge %[[TRG]](%cond, %idx) : i1, i32 {
-// CHECK-NEXT:  ^bb0(%[[ARGCOND:.*]]: i1, %[[ARGIDX:.*]]: i32):
-// CHECK-DAG:     %[[SHARED:.*]] = sim.fmt.dec %[[ARGIDX]] : i32
-// CHECK-DAG:     %[[MSGPFX:.*]] = sim.fmt.literal "value="
-// CHECK-DAG:     %[[FILEPFX:.*]] = sim.fmt.literal "out_"
-// CHECK-DAG:     %[[FILESFX:.*]] = sim.fmt.literal ".log"
-// CHECK-DAG:     %[[MSG:.*]] = sim.fmt.concat (%[[MSGPFX]], %[[SHARED]])
-// CHECK-DAG:     %[[FNAME:.*]] = sim.fmt.concat (%[[FILEPFX]], %[[SHARED]], %[[FILESFX]])
-// CHECK-DAG:     %[[FILE:.*]] = sim.get_file %[[FNAME]]
-// CHECK:         scf.if %[[ARGCOND]] {
-// CHECK-NEXT:      sim.proc.print %[[MSG]] to %[[FILE]]
-// CHECK-NEXT:    }
-// CHECK-NEXT:  }
-hw.module @shared_fmt_between_print_and_get_file(
-  in %clk: !seq.clock, in %cond: i1, in %idx: i32) {
-  %shared = sim.fmt.dec %idx : i32
-  %msgPrefix = sim.fmt.literal "value="
-  %msg = sim.fmt.concat (%msgPrefix, %shared)
-
-  %filePrefix = sim.fmt.literal "out_"
-  %fileSuffix = sim.fmt.literal ".log"
-  %fileName = sim.fmt.concat (%filePrefix, %shared, %fileSuffix)
-  %file = sim.get_file %fileName
-
-  sim.print %msg on %clk if %cond to %file
-}

test/Dialect/Sim/round-trip.mlir

@@ -102,8 +102,8 @@ func.func @DynamicStrings(%idx: i32) {
   return
 }
 
-// CHECK-LABEL: hw.module @PrintFormattedWithStream
-hw.module @PrintFormattedWithStream(in %clock: !seq.clock, in %condition: i1, in %idx: i32) {
+// CHECK-LABEL: hw.module @ProceduralPrintWithGetFile
+hw.module @ProceduralPrintWithGetFile(in %clock: !seq.clock, in %condition: i1, in %idx: i32) {
   // CHECK: %[[FMT:.*]] = sim.fmt.literal "literal string"
   %str = sim.fmt.literal "literal string"
   // CHECK: %[[FN0:.*]] = sim.fmt.literal "output_"
@@ -114,12 +114,15 @@ hw.module @PrintFormattedWithStream(in %clock: !seq.clock, in %condition: i1, in
   %fn2 = sim.fmt.literal ".txt"
   // CHECK: %[[FNAME:.*]] = sim.fmt.concat (%[[FN0]], %[[FN1]], %[[FN2]])
   %fileName = sim.fmt.concat (%fn0, %fn1, %fn2)
-  // CHECK: %[[FILE:.*]] = sim.get_file %[[FNAME]]
-  %file = sim.get_file %fileName
   // CHECK: sim.print %[[FMT]] on %clock if %condition
   sim.print %str on %clock if %condition
-  // CHECK: sim.print %[[FMT]] on %clock if %condition to %[[FILE]]
-  sim.print %str on %clock if %condition to %file
+  // CHECK: sim.triggered %clock if %condition {
+  sim.triggered %clock if %condition {
+    // CHECK: %[[FILE:.*]] = sim.get_file %[[FNAME]]
+    %file = sim.get_file %fileName
+    // CHECK: sim.proc.print %[[FMT]] to %[[FILE]]
+    sim.proc.print %str to %file
+  }
 }
 
 // CHECK-LABEL: hw.module @ProceduralPrint

test/Dialect/Sim/sim-errors.mlir

@@ -48,6 +48,14 @@ hw.module @procedural_ops_terminate() {
 
 // -----
 
+hw.module @procedural_ops_get_file() {
+  %name = sim.fmt.literal "out.log"
+  // expected-error @below {{must not be in a non-procedural region}}
+  %file = sim.get_file %name
+}
+
+// -----
+
 hw.module @nonprocedural_ops_print(in %trigger : i1, in %clock : !seq.clock, in %cond : i1) {
   hw.triggered posedge %trigger {
     %lit = sim.fmt.literal "Nope"