add SYNTHESIS guard

Author: nanjo712

lib/Conversion/SimToSV/SimToSV.cpp

@@ -65,6 +65,7 @@ struct SimConversionState {
   bool usedSynthesisMacro = false;
   bool usedFileDescriptorRuntime = false;
   SetVector<StringAttr> dpiCallees;
+  llvm::SmallDenseMap<Block *, sv::IfDefOp> synthesisGuards;
 };
 
 struct SimTypeConverter : public TypeConverter {
@@ -267,14 +268,27 @@ static LogicalResult convert(PauseOp op, PatternRewriter &rewriter) {
   return success();
 }
 
-class TriggeredLowering : public OpConversionPattern<TriggeredOp> {
+class TriggeredLowering : public SimConversionPattern<TriggeredOp> {
 public:
-  using OpConversionPattern<TriggeredOp>::OpConversionPattern;
+  using SimConversionPattern<TriggeredOp>::SimConversionPattern;
 
   LogicalResult
   matchAndRewrite(TriggeredOp op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op.getLoc();
+    state.usedSynthesisMacro = true;
+
+    auto [it, inserted] = state.synthesisGuards.try_emplace(op->getBlock());
+    auto ifdefOp = it->second;
+    if (!inserted) {
+      ifdefOp->moveBefore(op);
+    } else {
+      ifdefOp = sv::IfDefOp::create(
+          rewriter, loc, "SYNTHESIS", [] {}, [] {});
+      it->second = ifdefOp;
+    }
+    rewriter.setInsertionPointToEnd(ifdefOp.getElseBlock());
+
     auto trigger = seq::FromClockOp::create(rewriter, loc, adaptor.getClock());
     auto alwaysOp = sv::AlwaysOp::create(
         rewriter, loc, ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
@@ -869,7 +883,7 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
       patterns.add<ClockedPauseOp>(convert);
       patterns.add<TerminateOp>(convert);
       patterns.add<PauseOp>(convert);
-      patterns.add<TriggeredLowering>(typeConverter, context);
+      patterns.add<TriggeredLowering>(context, state);
       patterns.add<DPICallLowering>(context, state);
       auto result = applyPartialConversion(module, target, std::move(patterns));
 

test/Conversion/SimToSV/triggered.mlir

@@ -6,9 +6,12 @@ hw.module @simple_triggered(in %clock : !seq.clock) {
     "some.user"() : () -> ()
   }
 
-  // CHECK: %[[CLOCK:.*]] = seq.from_clock %clock
-  // CHECK-NEXT: sv.always posedge %[[CLOCK]] {
-  // CHECK-NEXT:   "some.user"() : () -> ()
+  // CHECK: sv.ifdef @SYNTHESIS {
+  // CHECK-NEXT: } else {
+  // CHECK-NEXT:   %[[CLOCK:.*]] = seq.from_clock %clock
+  // CHECK-NEXT:   sv.always posedge %[[CLOCK]] {
+  // CHECK-NEXT:     "some.user"() : () -> ()
+  // CHECK-NEXT:   }
   // CHECK-NEXT: }
 }
 
@@ -19,34 +22,43 @@ hw.module @conditional_triggered(
     "some.user"() : () -> ()
   }
 
-  // CHECK: %[[CLOCK:.*]] = seq.from_clock %clock
-  // CHECK-NEXT: sv.always posedge %[[CLOCK]] {
-  // CHECK-NEXT:   sv.if %en {
-  // CHECK-NEXT:     "some.user"() : () -> ()
+  // CHECK: sv.ifdef @SYNTHESIS {
+  // CHECK-NEXT: } else {
+  // CHECK-NEXT:   %[[CLOCK:.*]] = seq.from_clock %clock
+  // CHECK-NEXT:   sv.always posedge %[[CLOCK]] {
+  // CHECK-NEXT:     sv.if %en {
+  // CHECK-NEXT:       "some.user"() : () -> ()
+  // CHECK-NEXT:     }
   // CHECK-NEXT:   }
   // CHECK-NEXT: }
 }
 
 // CHECK-LABEL: hw.module @multiple_triggered
 hw.module @multiple_triggered(
-    in %clock : !seq.clock, in %en : i1) {
+    in %clock : !seq.clock) {
 
   sim.triggered %clock {
     "some.user"() : () -> ()
   }
 
-  sim.triggered %clock if %en {
+  %late_cond = "some.value"() : () -> i1
+
+  sim.triggered %clock if %late_cond {
     "some.user"() : () -> ()
   }
 
-  // CHECK: %[[CLOCK0:.*]] = seq.from_clock %clock
-  // CHECK-NEXT: sv.always posedge %[[CLOCK0]] {
-  // CHECK-NEXT:   "some.user"() : () -> ()
-  // CHECK-NEXT: }
-  // CHECK: %[[CLOCK1:.*]] = seq.from_clock %clock
-  // CHECK-NEXT: sv.always posedge %[[CLOCK1]] {
-  // CHECK-NEXT:   sv.if %en {
+  // CHECK: %[[LATE:.*]] = "some.value"() : () -> i1
+  // CHECK-NEXT: sv.ifdef @SYNTHESIS {
+  // CHECK-NEXT: } else {
+  // CHECK-NEXT:   %[[CLOCK0:.*]] = seq.from_clock %clock
+  // CHECK-NEXT:   sv.always posedge %[[CLOCK0]] {
   // CHECK-NEXT:     "some.user"() : () -> ()
   // CHECK-NEXT:   }
+  // CHECK-NEXT:   %[[CLOCK1:.*]] = seq.from_clock %clock
+  // CHECK-NEXT:   sv.always posedge %[[CLOCK1]] {
+  // CHECK-NEXT:     sv.if %[[LATE]] {
+  // CHECK-NEXT:       "some.user"() : () -> ()
+  // CHECK-NEXT:     }
+  // CHECK-NEXT:   }
   // CHECK-NEXT: }
 }