[Sim] Introduce sim.triggered op (#10450)

Author: nanjo712

include/circt/Dialect/Sim/SimOps.td

@@ -1146,4 +1146,31 @@ def PauseOp : SimOp<"pause", [ProceduralOp]> {
   }];
 }
 
+def TriggeredOp : SimOp<"triggered", [
+    SingleBlock, NoTerminator, NonProceduralOp, ProceduralRegion]> {
+  let summary = "A procedural region triggered on a clock edge";
+  let description = [{
+    A procedural region that executes on the rising edge of the given clock.
+    An optional 1-bit condition can be provided to guard execution of the
+    region on that clock edge.
+  }];
+
+  let arguments = (ins ClockType:$clock, Optional<I1>:$condition);
+  let regions = (region SizedRegion<1>:$body);
+  let assemblyFormat = [{
+    $clock (`if` $condition^)? $body attr-dict
+  }];
+
+  let extraClassDeclaration = [{
+    Block *getBodyBlock() { return &getBody().front(); }
+  }];
+
+  let skipDefaultBuilders = 1;
+  let builders = [
+    OpBuilder<(ins
+      "Value":$clock,
+      CArg<"Value", "mlir::Value()">:$condition)>
+  ];
+}
+
 #endif // CIRCT_DIALECT_SIM_SIMOPS_TD

lib/Dialect/Sim/SimOps.cpp

@@ -757,6 +757,20 @@ LogicalResult QueueConcatOp::verify() {
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// TriggeredOp
+//===----------------------------------------------------------------------===//
+
+void TriggeredOp::build(OpBuilder &builder, OperationState &odsState,
+                        Value clock, Value condition) {
+  odsState.addOperands(clock);
+  if (condition)
+    odsState.addOperands(condition);
+
+  auto *region = odsState.addRegion();
+  region->push_back(new Block());
+}
+
 //===----------------------------------------------------------------------===//
 // TableGen generated logic.
 //===----------------------------------------------------------------------===//

test/Dialect/Sim/round-trip.mlir

@@ -145,6 +145,26 @@ hw.module @ProceduralPrint(in %trigger: i1, in %condition: i1) {
   }
 }
 
+// CHECK-LABEL: hw.module @SimTriggered
+hw.module @SimTriggered(in %clock: !seq.clock, in %condition: i1) {
+  // CHECK: %[[MSG0:.*]] = sim.fmt.literal "tick"
+  %msg0 = sim.fmt.literal "tick"
+  // CHECK: %[[MSG1:.*]] = sim.fmt.literal "tock"
+  %msg1 = sim.fmt.literal "tock"
+
+  // CHECK: sim.triggered %clock {
+  sim.triggered %clock {
+    // CHECK: sim.proc.print %[[MSG0]]
+    sim.proc.print %msg0
+  }
+
+  // CHECK: sim.triggered %clock if %condition {
+  sim.triggered %clock if %condition {
+    // CHECK: sim.proc.print %[[MSG1]]
+    sim.proc.print %msg1
+  }
+}
+
 // CHECK-LABEL: hw.module @StdoutAndStderr
 hw.module @StdoutAndStderr(in %clock: !seq.clock, in %condition: i1) {
   // CHECK: %[[STDOUT_STR:.*]] = sim.fmt.literal "Hello, stdout!"