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[LTL] Make PastOp clock operand mandatory
1 parent 5ae6aef commit 34e393b

11 files changed

Lines changed: 10 additions & 66 deletions

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include/circt/Dialect/FIRRTL/FIRRTLExpressions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1823,9 +1823,9 @@ def LTLEventuallyIntrinsicOp : UnaryLTLIntrinsicOp<"eventually">;
18231823
def LTLPastIntrinsicOp : LTLIntrinsicOp<"past"> {
18241824
let arguments = (ins NonConstUInt1Type:$input,
18251825
I64Attr:$delay,
1826-
Optional<ClockType>:$clock);
1826+
ClockType:$clock);
18271827
let assemblyFormat = [{
1828-
$input `,` $delay (`,` $clock^)? attr-dict `:`
1828+
$input `,` $delay `,` $clock attr-dict `:`
18291829
functional-type(operands, results)
18301830
}];
18311831
}

include/circt/Dialect/LTL/LTLOps.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,16 +111,16 @@ def PastOp : LTLOp<"past", [TypesMatchWith<"input and result types must match",
111111
let arguments = (ins
112112
HWIntegerType:$input,
113113
I64Attr:$delay,
114-
Optional<I1>:$clk);
114+
I1:$clk);
115115
let results = (outs HWIntegerType:$result);
116116
let assemblyFormat = [{
117-
$input `,` $delay (`clk` $clk^)? attr-dict `:` type($input)
117+
$input `,` $delay `clk` $clk attr-dict `:` type($input)
118118
}];
119119

120120
let summary = "Observe the sequence $delay cycles earlier.";
121121
let description = [{
122122
Semantically works like `ltl.delay %seq, -$delay, 0`, clocked by the
123-
optional `$clk` operand if given.
123+
`$clk` operand.
124124
}];
125125
}
126126

lib/Conversion/FIRRTLToHW/LowerToHW.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4745,9 +4745,7 @@ LogicalResult FIRRTLLowering::visitExpr(LTLEventuallyIntrinsicOp op) {
47454745
}
47464746

47474747
LogicalResult FIRRTLLowering::visitExpr(LTLPastIntrinsicOp op) {
4748-
Value clk;
4749-
if (op.getClock())
4750-
clk = getLoweredNonClockValue(op.getClock());
4748+
Value clk = getLoweredNonClockValue(op.getClock());
47514749
return setLoweringToLTL<ltl::PastOp>(op, getLoweredValue(op.getInput()),
47524750
op.getDelayAttr(), clk);
47534751
}

lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -380,11 +380,11 @@ class CirctLTLPastConverter : public IntrinsicConverter {
380380
using IntrinsicConverter::IntrinsicConverter;
381381

382382
bool check(GenericIntrinsic gi) override {
383-
if (gi.hasNInputs(1, 1) || gi.sizedInput<UIntType>(0, 1) ||
383+
if (gi.hasNInputs(2) || gi.sizedInput<UIntType>(0, 1) ||
384384
gi.sizedOutput<UIntType>(1) || gi.namedIntParam("delay") ||
385385
gi.hasNParam(1))
386386
return true;
387-
if (gi.op.getNumOperands() > 1 && gi.typedInput<ClockType>(1))
387+
if (gi.typedInput<ClockType>(1))
388388
return true;
389389
return false;
390390
}
@@ -394,9 +394,7 @@ class CirctLTLPastConverter : public IntrinsicConverter {
394394
auto delay = rewriter.getI64IntegerAttr(
395395
gi.getParamValue<IntegerAttr>("delay").getValue().getZExtValue());
396396
auto operands = adaptor.getOperands();
397-
Value clock;
398-
if (operands.size() > 1)
399-
clock = operands[1];
397+
Value clock = operands[1];
400398
rewriter.replaceOpWithNewOp<LTLPastIntrinsicOp>(
401399
gi.op, gi.op.getResultTypes(), operands[0], delay, clock);
402400
}

lib/Dialect/FIRRTL/FIRRTLIntrinsics.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -260,7 +260,7 @@ def CirctLTLPast : FIRRTLIntrinsic {
260260
| Argument | Type | Description |
261261
| -------- | ------- | ------------------------- |
262262
| in | UInt<1> | input boolean |
263-
| clock | Clock | clock for delay; optional |
263+
| clock | Clock | clock for delay |
264264

265265
| Result | Type | Description |
266266
| ------ | ------- | ---------------------- |

test/Conversion/FIRRTLToHW/intrinsics.mlir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,6 @@ firrtl.circuit "Intrinsics" {
104104
// CHECK-NEXT: [[E0:%.+]] = ltl.eventually [[I0]] : !ltl.property
105105
%e0 = firrtl.int.ltl.eventually %i0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
106106

107-
// CHECK-NEXT: [[P0:%.+]] = ltl.past %a, 1 : i1
108-
%p0 = firrtl.int.ltl.past %a, 1 : (!firrtl.uint<1>) -> !firrtl.uint<1>
109107
// CHECK-NEXT: [[P1:%.+]] = ltl.past %b, 3 clk [[CLK]] : i1
110108
%p1 = firrtl.int.ltl.past %b, 3, %clk : (!firrtl.uint<1>, !firrtl.clock) -> !firrtl.uint<1>
111109

test/Conversion/LTLToCore/assume-first-clock-errors.mlir

Lines changed: 0 additions & 7 deletions
This file was deleted.

test/Conversion/LTLToCore/assume-first-clock.mlir

Lines changed: 0 additions & 30 deletions
This file was deleted.

test/Conversion/LTLToCore/ltl-to-core-errors.mlir

Lines changed: 0 additions & 6 deletions
This file was deleted.

test/Dialect/FIRRTL/lower-intrinsics.mlir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,6 @@ firrtl.circuit "Foo" {
7777
// CHECK-NEXT: firrtl.int.ltl.eventually %in0 :
7878
firrtl.int.generic "circt_ltl_eventually" %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
7979

80-
// CHECK-NEXT: firrtl.int.ltl.past %in0, 42 :
81-
firrtl.int.generic "circt_ltl_past" <delay: i64 = 42> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
8280
// CHECK-NEXT: firrtl.int.ltl.past %in0, 42, %clk :
8381
firrtl.int.generic "circt_ltl_past" <delay: i64 = 42> %in0, %clk : (!firrtl.uint<1>, !firrtl.clock) -> !firrtl.uint<1>
8482

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